`timescale 1ns / 1ps

module RFwithALU(
	Read1,
   Read2,
   WriteReg,
   WriteData,
   RegWrite,
   Clock,

	ALUOp,
	FuncCode,
	ALUOut,
	Zero
   );

	input [4:0] Read1;
   input [4:0] Read2;
   input [4:0] WriteReg;
   input [31:0] WriteData;
   input RegWrite;
   input Clock;

   wire [31:0] Data1;
   wire [31:0] Data2;
	wire [3:0] ALUCtl;

	input [1:0] ALUOp;
   input [5:0] FuncCode;
   output [31:0] ALUOut;
   output Zero;

	RegisterFile rf(Read1, Read2, WriteReg, WriteData, RegWrite, Clock, Data1, Data2);

	ALUwithControl aluCtrl(ALUOp, FuncCode, Data1, Data2, ALUOut, Zero);

endmodule

`timescale 1ns / 1ps

`timescale 1ns / 1ps
module RegisterFile(
		input [4:0] Read1,
		input [4:0] Read2,
		input [4:0] WriteReg,
		input [31:0] WriteData,
		input RegWrite,
		input Clock,
		output [31:0] Data1,
		input [31:0] Data2
   );

	integer i;
	reg [31:0] RF[0:31];
	initial  begin //32 registers each 32 bits long
		for (i=0; i<32; i=i+1) begin
			RF[i] <= 32'h00000000;
		end
	end
	assign Data1 = RF[Read1];
	assign Data2 = RF[Read2];
	always begin @(posedge Clock)
		if (RegWrite == 1)RF[WriteReg] <= WriteData;
	end
endmodule

module ALUwithControl (ALUOp, FuncCode, A, B, ALUOut, Zero);

   input [1:0] ALUOp;
   input [5:0] FuncCode;
   input [31:0] A;
   input [31:0] B;
   input [31:0] ALUOut;
   input Zero;

   wire [3:0] ALUctl;

	ALUControl aluControl(ALUOp, FuncCode, ALUctl);
	MIPSALU alu(ALUctl, A, B, ALUOut, Zero);

endmodule