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  1. `timescale 1ns / 1ps
  2.  
  3. module RFwithALU(
  4.     Read1,
  5.    Read2,
  6.    WriteReg,
  7.    WriteData,
  8.    RegWrite,
  9.    Clock,
  10.    
  11.     ALUOp,
  12.     FuncCode,
  13.     ALUOut,
  14.     Zero
  15.    );
  16.  
  17.     input [4:0] Read1;
  18.    input [4:0] Read2;
  19.    input [4:0] WriteReg;
  20.    input [31:0] WriteData;
  21.    input RegWrite;
  22.    input Clock;
  23.    
  24.    wire [31:0] Data1;
  25.    wire [31:0] Data2;
  26.     wire [3:0] ALUCtl;
  27.    
  28.     input [1:0] ALUOp;
  29.    input [5:0] FuncCode;
  30.    output [31:0] ALUOut;
  31.    output Zero;
  32.    
  33.     RegisterFile rf(Read1, Read2, WriteReg, WriteData, RegWrite, Clock, Data1, Data2);
  34.    
  35.     ALUwithControl aluCtrl(ALUOp, FuncCode, Data1, Data2, ALUOut, Zero);
  36.    
  37. endmodule
  38.  
  39. `timescale 1ns / 1ps
  40.  
  41. `timescale 1ns / 1ps
  42. module RegisterFile(
  43.         input [4:0] Read1,
  44.         input [4:0] Read2,
  45.         input [4:0] WriteReg,
  46.         input [31:0] WriteData,
  47.         input RegWrite,
  48.         input Clock,
  49.         output [31:0] Data1,
  50.         input [31:0] Data2
  51.    );
  52.  
  53.     integer i;
  54.     reg [31:0] RF[0:31];
  55.     initial  begin //32 registers each 32 bits long
  56.         for (i=0; i<32; i=i+1) begin
  57.             RF[i] <= 32'h00000000;
  58.         end
  59.     end
  60.     assign Data1 = RF[Read1];
  61.     assign Data2 = RF[Read2];
  62.     always begin @(posedge Clock)
  63.         if (RegWrite == 1)RF[WriteReg] <= WriteData;
  64.     end
  65. endmodule
  66.  
  67. module ALUwithControl (ALUOp, FuncCode, A, B, ALUOut, Zero);
  68.  
  69.    input [1:0] ALUOp;
  70.    input [5:0] FuncCode;
  71.    input [31:0] A;
  72.    input [31:0] B;
  73.    input [31:0] ALUOut;
  74.    input Zero;
  75.    
  76.    wire [3:0] ALUctl;
  77.      
  78.     ALUControl aluControl(ALUOp, FuncCode, ALUctl);
  79.     MIPSALU alu(ALUctl, A, B, ALUOut, Zero);
  80.    
  81. endmodule
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