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-- Company:
-- Engineer:
--
-- Create Date:    11:39:15 01/15/2019
-- Design Name:
-- Module Name:    picture1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity picture1 is
    Port ( PIX_X : in  STD_LOGIC_VECTOR (9 downto 0);
           PIX_Y : in  STD_LOGIC_VECTOR (8 downto 0);
           RGB : out  STD_LOGIC_VECTOR (2 downto 0));
end picture1;

architecture Behavioral of picture1 is
begin

    -- Static picture:
    -- left side is RED ("100")
    -- right side is BLUE ("001")
    get_color : process(PIX_X, PIX_Y)
    begin
        if (PIX_X < 320) then
            RGB <= "100";
        else
            RGB <= "001";
        end if;
    end process get_color;

end Behavioral;