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BillNace

F17 18-240 L01 Slide 23: Illustrating Execution Model

Jan 1st, 2018
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  1. module sop
  2.     (output logic f,
  3.      input  logic a, b, c, d);
  4.  
  5.   nand #5 g1(f1, a, b),
  6.           g2(f2, c, d),
  7.           g3(f, f1, f2);
  8.  
  9. endmodule: sop
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