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- //module Zadanie1(SW, LEDR);
- // input [9:0] SW;
- // output [9:0] LEDR;
- // assign LEDR = SW;
- //endmodule
- //module Zadanie1 (
- // input [3:0] KEY,
- // output [3:0] LEDR);
- // assign LEDR = ~KEY;
- //endmodule
- module mux_2_1_1_bit (
- input x, y, s,
- output m);
- assign m = (~s & x) | (s & y);
- endmodule
- //module part1 (
- // input [1:0] SW,
- // input [0:0] KEY,
- // output [0:0] LEDR);
- //
- // Zadanie1 nazwa (SW[0], SW[1], KEY[0], LEDR[0]);
- //
- //endmodule
- module mux_2_1_4_bits (
- input [3:0] X, Y,
- input s,
- output [3:0] M
- );
- mux_2_1_1_bit ex0 (X[0], Y[0], s, M[0]);
- mux_2_1_1_bit ex1 (X[1], Y[1], s, M[1]);
- mux_2_1_1_bit ex2 (X[2], Y[2], s, M[2]);
- mux_2_1_1_bit ex3 (X[3], Y[3], s, M[3]);
- endmodule
- //module part1 (
- // input [7:0] SW,
- // input [0:0] KEY,
- // output [3:0] LEDR
- //);
- //
- // mux_2_1_4_bits ex (SW[3:0], SW[7:4], KEY[0], LEDR[3:0]);
- //
- //endmodule
- module mux_4_1_1_bit (
- input [3:0] X,
- input [1:0] S,
- output [0:0] M
- );
- wire [1:0] P;
- mux_2_1_1_bit ex0 (X[0], X[1], S[0], P[0]);
- mux_2_1_1_bit ex1 (X[2], X[3], S[0], P[1]);
- mux_2_1_1_bit ex2 (P[0], P[1], S[1], M[0]);
- endmodule
- //module part1 (
- // input [3:0] SW,
- // input [1:0] KEY,
- // output [0:0] LEDR
- //);
- //
- // mux_4_1_1_bit ex (SW[3:0], KEY[1:0], LEDR[0]);
- //
- //endmodule
- module mux_4_1_2_bits (
- input [1:0] U,
- input [1:0] V,
- input [1:0] W,
- input [1:0] X,
- input [1:0] S,
- output [1:0] M
- );
- mux_4_1_1_bit ex0 ({X[0], W[0], V[0], U[0]}, S[1:0], M[0]);
- mux_4_1_1_bit ex1 ({X[1], W[1], V[1], U[1]}, S[1:0], M[1]);
- endmodule
- //module part1 (
- // input [7:0] SW,
- // input [1:0] KEY,
- // output [1:0] LEDR
- //);
- //
- // mux_4_1_2_bits ex (SW[7:0], KEY[1:0], LEDR[1:0]);
- //
- //endmodule
- module decoder_7_seg (
- input [1:0] C,
- output [6:0] H
- );
- assign H[0] = ~C[0] | C[1];
- assign H[1] = C[0];
- assign H[2] = C[0];
- assign H[3] = C[1];
- assign H[4] = C[1];
- assign H[5] = ~C[0] | C[1];
- assign H[6] = C[1];
- endmodule
- //
- //module part1 (
- // input [1:0] SW,
- // output [6:0] HEX0
- //);
- //
- // decoder_7_seg ex (SW[1:0], HEX0[6:0]);
- //
- //endmodule
- //
- //module part1 ( // zad 8
- // input [9:0] SW,
- // output [6:0] HEX0,
- // output [9:0] LEDR
- //);
- //
- // wire [1:0] P;
- //
- // mux_4_1_2_bits ex0 (SW[7:6], SW[5:4], SW[3:2], SW[1:0], SW[9:8], P[1:0]);
- // decoder_7_seg ex1 (P[1:0], HEX0[6:0]);
- //
- // assign LEDR = SW;
- //
- //endmodule
- module word_4_symbols (
- input [1:0] W1,
- input [1:0] W2,
- input [1:0] W3,
- input [1:0] W4,
- output [6:0] H1,
- output [6:0] H2,
- output [6:0] H3,
- output [6:0] H4
- );
- decoder_7_seg d1 (W1[1:0], H1[6:0]);
- decoder_7_seg d2 (W2[1:0], H2[6:0]);
- decoder_7_seg d3 (W3[1:0], H3[6:0]);
- decoder_7_seg d4 (W4[1:0], H4[6:0]);
- endmodule
- //module part1 (
- // input [7:0] SW,
- // output [6:0] HEX0,
- // output [6:0] HEX1,
- // output [6:0] HEX2,
- // output [6:0] HEX3
- //);
- //
- // word_4_symbols ex (SW[1:0], SW[3:2], SW[5:4], SW[7:6], HEX0[6:0], HEX1[6:0], HEX2[6:0], HEX3[6:0]);
- //
- //endmodule
- //
- //module
- //module word_4_symbols_with_spaces (
- // input [1:0] SPACE_POS,
- // output reg[6:0] H1, H2, H3, H4, H5
- //);
- //
- // always @(*)
- // case(SPACE_POS[1:0])
- // 2'o0: begin
- // H1 = 7'b1111111;
- // H2 = 7'b1000010;
- // H3 = 7'b0110000;
- // H4 = 7'b1001111;
- // H5 = 7'b1000010;
- // end
- // 2'o1: begin
- // H1 = 7'b1000010;
- // H2 = 7'b1111111;
- // H3 = 7'b0110000;
- // H4 = 7'b1001111;
- // H5 = 7'b1000010;
- // end
- // 2'o2: begin
- // H1 = 7'b1000010;
- // H2 = 7'b1000010;
- // H3 = 7'b1111111;
- // H4 = 7'b1001111;
- // H5 = 7'b1000010;
- // end
- // 2'o3: begin
- // H1 = 7'b1000010;
- // H2 = 7'b1000010;
- // H3 = 7'b0110000;
- // H4 = 7'b1111111;
- // H5 = 7'b1000010;
- // end
- // endcase
- //
- //
- //endmodule
- //
- //module part1 (
- // input [9:0]SW,
- // output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5
- //);
- //
- // word_4_symbols_with_spaces(SW[1:0], SW[9:2]);
- //
- //endmodule
- module part1(
- input [9:0] SW,
- output reg [0:6] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);
- always @(*)
- case (SW[9:7])
- 3'o0: begin
- HEX0 = 7'b0000001;
- HEX1 = 7'b1001111;
- HEX2 = 7'b0110000;
- HEX3 = 7'b1000010;
- HEX4 = 7'b1111111;
- HEX5 = 7'b1111111;
- end
- 3'o1: begin
- HEX1 = 7'b0000001;
- HEX2 = 7'b1001111;
- HEX3 = 7'b0110000;
- HEX4 = 7'b1000010;
- HEX5 = 7'b1111111;
- HEX0 = 7'b1111111;
- end
- 3'o2: begin
- HEX2 = 7'b0000001;
- HEX3 = 7'b1001111;
- HEX4 = 7'b0110000;
- HEX5 = 7'b1000010;
- HEX0 = 7'b1111111;
- HEX1 = 7'b1111111;
- end
- 3'o3: begin
- HEX3 = 7'b0000001;
- HEX4 = 7'b1001111;
- HEX5 = 7'b0110000;
- HEX0 = 7'b1000010;
- HEX1 = 7'b1111111;
- HEX2 = 7'b1111111;
- end
- 3'o4: begin
- HEX4 = 7'b0000001;
- HEX5 = 7'b1001111;
- HEX0 = 7'b0110000;
- HEX1 = 7'b1000010;
- HEX2 = 7'b1111111;
- HEX3 = 7'b1111111;
- end
- 3'o5: begin
- HEX5 = 7'b0000001;
- HEX0 = 7'b1001111;
- HEX1 = 7'b0110000;
- HEX2 = 7'b1000010;
- HEX3 = 7'b1111111;
- HEX4 = 7'b1111111;
- end
- endcase
- endmodule
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