module question2(clock, resetn, s, done, DA, DB, A, B, P);
input clock, resetn, s;
wire z, b_0;
input [7:0] DA;
input [3:0] DB;
output reg done;
output [7:0] A;
output [7:0] P;
output [3:0] B;

reg E, L, EP, sclrP;

localparam S1 = 2'd1, S2 = 2'd2, S3 = 2'd3;
reg [1:0] currentState, nextState;

moduleA modA(0, L, E, DA, A);
moduleB modB(0, L, E, B, b_0, z);
moduleP modP(EP, sclrP, A, P);

initial
begin
    currentState = S1;
end

always @ (posedge clock)
begin
    currentState = nextState;
end

always @  (resetn, s, z, b_0)
begin
    E = 1'b0;
    L = 1'b0;
    EP = 1'b0;
    sclrP = 1'b0;

    if (~resetn)
    begin
        nextState = S1;
    end

    if (currentState == S1)
    begin
        sclrP = 1;
        EP = 1;
        if (s)
        begin
            L = 1;
            E = 1;
            nextState = S2;
        end
        else
        begin
            nextState = S1;
        end
    end

    if (currentState == S2)
    begin
        E = 1;
        if (z)
        begin
            nextState = S3;
        end
        else
        begin
            if (b_0)
            begin
                EP = 1;
            end
            nextState = S2;
        end
    end

    if (currentState == S3)
    begin
        done = 1;
        if (s)
        begin
            nextState = S3;
        end
        else
        begin
            nextState = S1;
        end
    end
end

endmodule

module moduleA(din, s_l, E, DA, A_out);
    input din, s_l, E;
    input [7:0] DA;
    output reg [7:0] A_out;

    always @ ( * )
    begin
        if (E)
        begin
            if (s_l)
                // Load data in from file
            begin
            end
            else
            begin
                A_out = {DA[7:1], 1'b0};// (DA << 1);     // left shift
            end
        end
    end
endmodule

module moduleB(din, s_l, E, B, b_0, z);
    input din, s_l, E;
    output reg [3:0] B;
    output reg b_0, z;

    always @ ( * )
    begin
        if (E)
        begin
            if (s_l)
            begin
                // Load data in from file
            end
            else
            begin
                B = B >> 1;     // right shift
                z = !(B[3] | B[2] | B[1] | B[0]);
                b_0 = B[0];
            end
        end
    end
endmodule

module moduleP(E, sclr, A, P);
    input E, sclr;
    input [7:0] A;
    output reg [7:0] P;

    always @ ( * )
    begin
        if (E)
        begin
            if (sclr)
            begin
                P <= 8'b0;
            end
            else
                P <= A + P;
            begin

            end
        end
    end
endmodule

module question2_tb();
    reg clk, resetn, s;
    reg [7:0] DA;
    reg [3:0] DB;
    reg [3:0] readData[0:63];
    reg [6:0] dataIndex;

    initial
    begin
        clk <= 0;
        resetn <= 0;
        s <= 0;
        DA <= 8'b0;
        DB <= 4'b0;
        $readmemb("C:/Users/Administrator/Desktop/Assignment3/Question2/Inputs.txt", readData);
    end

    question2 dut(.clock(clk), .resetn(resetn), .s(s), .done(done), .DA(DA), .DB(DB), .A(A), .B(B), .P(P));

    always
    begin
        #10
        clk <= ~clk;
    end

    always @(posedge clk)
    begin
        resetn <= readData[dataIndex][0];
        dataIndex <= dataIndex + 1;
        DA <= readData[dataIndex];
        dataIndex <= dataIndex + 1;
        DB <= readData[dataIndex];
        dataIndex <= dataIndex + 1;
        s <= readData[dataIndex][0];
        dataIndex <= dataIndex + 1;
    end
endmodule