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Jul 21st, 2018
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  1. Slice Logic Utilization:
  2. Number of Slice Registers: 64,340 out of 184,304 34%
  3. Number used as Flip Flops: 63,983
  4. Number used as Latches: 0
  5. Number used as Latch-thrus: 0
  6. Number used as AND/OR logics: 357
  7. Number of Slice LUTs: 54,520 out of 92,152 59%
  8. Number used as logic: 38,979 out of 92,152 42%
  9. Number using O6 output only: 23,844
  10. Number using O5 output only: 579
  11. Number using O5 and O6: 14,556
  12. Number used as ROM: 0
  13. Number used as Memory: 13,032 out of 21,680 60%
  14. Number used as Dual Port RAM: 0
  15. Number used as Single Port RAM: 0
  16. Number used as Shift Register: 13,032
  17. Number using O6 output only: 450
  18. Number using O5 output only: 0
  19. Number using O5 and O6: 12,582
  20. Number used exclusively as route-thrus: 2,509
  21. Number with same-slice register load: 1,870
  22. Number with same-slice carry load: 639
  23. Number with other load: 0
  24.  
  25. Slice Logic Distribution:
  26. Number of occupied Slices: 16,465 out of 23,038 71%
  27. Number of MUXCYs used: 22,156 out of 46,076 48%
  28. Number of LUT Flip Flop pairs used: 58,021
  29. Number with an unused Flip Flop: 11,231 out of 58,021 19%
  30. Number with an unused LUT: 3,501 out of 58,021 6%
  31. Number of fully used LUT-FF pairs: 43,289 out of 58,021 74%
  32. Number of slice register sites lost
  33. to control set restrictions: 0 out of 184,304 0%
  34.  
  35. A LUT Flip Flop pair for this architecture represents one LUT paired with
  36. one Flip Flop within a slice. A control set is a unique combination of
  37. clock, reset, set, and enable signals for a registered element.
  38. The Slice Logic Distribution report is not meaningful if the design is
  39. over-mapped for a non-slice resource or if Placement fails.
  40.  
  41. IO Utilization:
  42. Number of bonded IOBs: 26 out of 338 7%
  43. Number of LOCed IOBs: 26 out of 26 100%
  44. IOB Flip Flops: 3
  45.  
  46. Specific Feature Utilization:
  47. Number of RAMB16BWERs: 0 out of 268 0%
  48. Number of RAMB8BWERs: 0 out of 536 0%
  49. Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
  50. Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
  51. Number of BUFG/BUFGMUXs: 2 out of 16 12%
  52. Number used as BUFGs: 2
  53. Number used as BUFGMUX: 0
  54. Number of DCM/DCM_CLKGENs: 1 out of 12 8%
  55. Number used as DCMs: 0
  56. Number used as DCM_CLKGENs: 1
  57. Number of ILOGIC2/ISERDES2s: 3 out of 586 1%
  58. Number used as ILOGIC2s: 3
  59. Number used as ISERDES2s: 0
  60. Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
  61. Number of OLOGIC2/OSERDES2s: 0 out of 586 0%
  62. Number of BSCANs: 0 out of 4 0%
  63. Number of BUFHs: 0 out of 384 0%
  64. Number of BUFPLLs: 0 out of 8 0%
  65. Number of BUFPLL_MCBs: 0 out of 4 0%
  66. Number of DSP48A1s: 0 out of 180 0%
  67. Number of ICAPs: 0 out of 1 0%
  68. Number of MCBs: 0 out of 4 0%
  69. Number of PCILOGICSEs: 0 out of 2 0%
  70. Number of PLL_ADVs: 1 out of 6 16%
  71. Number of PMVs: 0 out of 1 0%
  72. Number of STARTUPs: 0 out of 1 0%
  73. Number of SUSPEND_SYNCs: 0 out of 1 0%
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