`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    17:06:27 02/18/2020
// Design Name:
// Module Name:    main
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
    // outputs
    DISP_SEG,
    DISP_SEL,
    // inputs
    SEL,
    ADJ,
    RST,
    PSE,
    CLK
    );

    input CLK;
    input PSE;
    input RST;
    input ADJ;
    input SEL;
    output [6:0] DISP_SEG;
    output [3:0] DISP_SEL;

    wire FAST_CLK;
    wire ONE_CLK;
    wire TWO_CLK;
    wire BLINK_CLK;
    wire RST_S;
    wire PSE_S;

    clock_divider clock_divider_(
        .CLK    (CLK),
        .FAST_CLK   (FAST_CLK),
        .ONE_CLK    (ONE_CLK),
        .TWO_CLK    (TWO_CLK),
        .BLINK_CLK  (BLINK_CLK)
        );

    debouncer debouncer_(
        .RST    (RST),
        .PSE    (PSE),
        .FAST_CLK   (FAST_CLK),
        .RST_S  (RST_S),
        .PSE_S  (PSE_S)
        );
endmodule