library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity equations is
port(
    A : in std_logic;
    B : in std_logic;
    C0 : in std_logic;
    C1 : in std_logic;
    C2 : in std_logic;
    C3 : in std_logic;
    C4 : in std_logic;
    C5 : in std_logic;
    Result : out std_logic_vector(5 downto 0));

end equations;

architecture Behavioral of equations is

begin
    Result(0) <= (A NAND B) AND C0;
    Result(1) <= (A NOR B) AND C1;
    Result(2) <= (A AND B) AND C2;
    Result(3) <= (A XOR B) AND C3;
    Result(4) <= ((A AND B) OR ((NOT A) AND (NOT B))) AND C4;
    Result(5) <= (((NOT A) AND B) XOR ((NOT A) OR B)) AND C5;

end Behavioral;