//binary_counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity binary_counter_test is
    Port ( clk_in : in  STD_LOGIC;
           count_out : out  STD_LOGIC_VECTOR (1 downto 0));
end binary_counter_test;

architecture Behavioral of binary_counter_test is
    signal clk_1hz : std_logic;                                                                         --TO DO 1 -> deklarirati signal clk_1Hz koji je tipa std_logic
    signal count_temp   :   std_logic_vector(1 downto 0);
begin

    divider_1Hz :   entity work.generic_divider generic map (100_000_000) port map (clk_in, clk_1hz);       --TO DO 2 -> instancirati generički djelitelj frekvencije tako da ulazni signal takta pretvori u signal takta frekvencije 1Hz
    counter :   entity work.binary_counter port map(clk_1hz, count_out);                            --TO DO 3 -> instancirati binarni brojač tako da broji frekvencijom od 1Hz i da povratnu vrijednost spremi u signal count_temp

end Behavioral;

// COUNTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity binary_counter is
    Port ( clk_in : in  STD_LOGIC;
           count_out : out  STD_LOGIC_VECTOR (1 downto 0));
end binary_counter;

architecture Behavioral of binary_counter is
signal count_temp : std_logic_vector(1 downto 0);                                                                   --TO DO 1 -> deklarirati signal count_temp koji je tipa std_logic i veličine je 2 bita
begin

    PROCESS(clk_in)

    BEGIN
        IF(clk_in'event and clk_in='1') THEN                                                        --TO DO 2 -> detektirati rastući brid signala takta clk_in
            count_temp<=count_temp+1;                                                           --TO DO 3 -> uvećati signal count_temp za 1
        END IF;
    END PROCESS;

                                                                        --TO DO 4 -> izlaznom signalu count_out pridružiti vrijednost signala count_temp
count_out<=count_temp;
end Behavioral;

// divider

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity generic_divider is
GENERIC
(
    N   :   INTEGER :=  50_000_000
);
PORT
(
    clk_in  :   IN  STD_LOGIC;
    clk_out :   OUT STD_LOGIC
);
end generic_divider;

architecture Behavioral of generic_divider is
    signal clk_t    :   STD_LOGIC;
begin

PROCESS(clk_in)
    variable temp   :   INTEGER RANGE 0 TO N;
BEGIN

    IF(clk_in'event and clk_in='1') THEN                                --TO DO 1   -> detektirati rastući brid signala takta clk_in
        temp:=temp+1;                                   --TO DO 2   -> varijablu temp uvećati za 1
        IF(temp >= N) THEN
            clk_t<=not clk_t;                               --TO DO 3   -> invertirati signal clk_t
            temp := 0;
        END IF;
    END IF;

END PROCESS;

clk_out <= clk_t;                                           --TO DO 4   ->  izlaznom signalu clk_out pridružiti vrijednost signala clk_t

end Behavioral;