[alarm@alarm ~]$ LIMA_SHADER_DEBUG=pp valgrind --leak-check=full --track-origins=yes ~/usr/bin/glmark2-es2-drm -b bump
==14759== Memcheck, a memory error detector
==14759== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.
==14759== Using Valgrind-3.13.0 and LibVEX; rerun with -h for copyright info
==14759== Command: /home/alarm/usr/bin/glmark2-es2-drm -b bump
==14759==
lima: enable shader PP debug
=======================================================
    glmark2 2017.07
=======================================================
    OpenGL Information
    GL_VENDOR:     lima
    GL_RENDERER:   Mali400
    GL_VERSION:    OpenGL ES 2.0 Mesa 18.1.0 (git-0456e777a2)
=======================================================
[bump] <default>:shader: MESA_SHADER_FRAGMENT
name: GLSL1
inputs: 1
outputs: 1
uniforms: 0
shared: 0
decl_var shader_in INTERP_MODE_NONE vec3 packed:Normal (VARYING_SLOT_VAR9.xyz, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 0, 0)
decl_function main returning void

impl main {
        decl_reg vec4 32 r0
        block block_0:
        /* preds: */
        vec4 32 ssa_0 = load_const (0x3dcccccd /* 0.100000 */, 0x3dcccccd /* 0.100000 */, 0x3dcccccd /* 0.100000 */, 0x3f800000 /* 1.000000 */)
        vec4 32 ssa_1 = load_const (0x3e23d70b /* 0.160000 */, 0x3e23d70b /* 0.160000 */, 0x3e23d70b /* 0.160000 */, 0x3f800000 /* 1.000000 */)
        vec3 32 ssa_2 = load_const (0x3ed105e0 /* 0.408248 */, 0x3ed105e0 /* 0.408248 */, 0x3f5105f1 /* 0.816497 */)
        vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */)
        vec1 32 ssa_4 = load_const (0x42c80000 /* 100.000000 */)
        vec4 32 ssa_5 = load_const (0x3f4ccccd /* 0.800000 */, 0x3f4ccccd /* 0.800000 */, 0x3f4ccccd /* 0.800000 */, 0x3f800000 /* 1.000000 */)
        vec3 32 ssa_6 = load_const (0x3f2aaaab /* 0.666667 */, 0x3f2aaaab /* 0.666667 */, 0x3eaaaaab /* 0.333333 */)
        vec3 32 ssa_7 = intrinsic load_input (ssa_3) () (0, 0) /* base=0 */ /* component=0 */   /* packed:Normal */
        vec1 32 ssa_8 = fmul ssa_7.x, ssa_7.x
        vec1 32 ssa_9 = fmul ssa_7.y, ssa_7.y
        vec1 32 ssa_10 = fadd ssa_8, ssa_9
        vec1 32 ssa_11 = fmul ssa_7.z, ssa_7.z
        vec1 32 ssa_12 = fadd ssa_10, ssa_11
        vec1 32 ssa_13 = frsq ssa_12
        vec1 32 ssa_14 = fmul ssa_7.x, ssa_13
        vec1 32 ssa_15 = fmul ssa_7.y, ssa_13
        vec1 32 ssa_16 = fmul ssa_7.z, ssa_13
        vec1 32 ssa_17 = fmul ssa_14, ssa_2.x
        vec1 32 ssa_18 = fmul ssa_15, ssa_2.y
        vec1 32 ssa_19 = fadd ssa_17, ssa_18
        vec1 32 ssa_20 = fmul ssa_16, ssa_2.z
        vec1 32 ssa_21 = fadd ssa_19, ssa_20
        vec1 32 ssa_22 = fmax ssa_21, ssa_3
        vec1 32 ssa_23 = flog2 ssa_22
        vec1 32 ssa_24 = fmul ssa_23, ssa_4
        vec1 32 ssa_25 = fexp2 ssa_24
        vec1 32 ssa_26 = fmul ssa_1.x, ssa_25
        vec1 32 ssa_27 = fmul ssa_1.y, ssa_25
        vec1 32 ssa_28 = fmul ssa_1.z, ssa_25
        vec1 32 ssa_29 = fadd ssa_0.x, ssa_26
        vec1 32 ssa_30 = fadd ssa_0.y, ssa_27
        vec1 32 ssa_31 = fadd ssa_0.z, ssa_28
        vec1 32 ssa_32 = fadd ssa_0.w, ssa_25
        vec1 32 ssa_33 = fmul ssa_14, ssa_6.x
        vec1 32 ssa_34 = fmul ssa_15, ssa_6.y
        vec1 32 ssa_35 = fadd ssa_33, ssa_34
        vec1 32 ssa_36 = fmul ssa_16, ssa_6.z
        vec1 32 ssa_37 = fadd ssa_35, ssa_36
        vec1 32 ssa_38 = fmax ssa_37, ssa_3
        vec1 32 ssa_39 = fmul ssa_5.x, ssa_38
        vec1 32 ssa_40 = fmul ssa_5.y, ssa_38
        vec1 32 ssa_41 = fmul ssa_5.z, ssa_38
        r0.x = fadd ssa_29, ssa_39
        r0.y = fadd ssa_30.x, ssa_40.x
        r0.z = fadd ssa_31.x, ssa_41.x
        r0.w = fadd ssa_32.x, ssa_38.x
        intrinsic store_output (r0, ssa_3) () (0, 15, 0) /* base=0 */ /* wrmask=xyzw */ /* component=0 */       /* gl_FragColor */
        /* succs: block_0 */
        block block_0:
}

========prog========
-------block------
st_col 46 new
  add 42 reg0
    add 29 ssa29
      const 0 ssa0
      mul 26 ssa26
        const 1 ssa1
        exp2 25 ssa25
          mul 24 ssa24
            log2 23 ssa23
              max 22 ssa22
                add 21 ssa21
                  add 19 ssa19
                    mul 17 ssa17
                      mul 14 ssa14
                        ld_var 7 ssa7
                        rsqrt 13 ssa13
                          add 12 ssa12
                            add 10 ssa10
                              mul 8 ssa8
                                ld_var 7 ssa7
                              mul 9 ssa9
                                ld_var 7 ssa7
                            mul 11 ssa11
                              ld_var 7 ssa7
                      const 2 ssa2
                    mul 18 ssa18
                      mul 15 ssa15
                        ld_var 7 ssa7
                        +rsqrt 13 ssa13
                      const 2 ssa2
                  mul 20 ssa20
                    mul 16 ssa16
                      ld_var 7 ssa7
                      +rsqrt 13 ssa13
                    const 2 ssa2
                const 3 ssa3
            const 4 ssa4
    mul 39 ssa39
      const 5 ssa5
      max 38 ssa38
        add 37 ssa37
          add 35 ssa35
            mul 33 ssa33
              +mul 14 ssa14
              const 6 ssa6
            mul 34 ssa34
              +mul 15 ssa15
              const 6 ssa6
          mul 36 ssa36
            +mul 16 ssa16
            const 6 ssa6
        const 3 ssa3
  add 43 reg0
    add 30 ssa30
      const 0 ssa0
      mul 27 ssa27
        const 1 ssa1
        +exp2 25 ssa25
    mul 40 ssa40
      const 5 ssa5
      +max 38 ssa38
  add 44 reg0
    add 31 ssa31
      const 0 ssa0
      mul 28 ssa28
        const 1 ssa1
        +exp2 25 ssa25
    mul 41 ssa41
      const 5 ssa5
      +max 38 ssa38
  add 45 reg0
    add 32 ssa32
      const 0 ssa0
      +exp2 25 ssa25
    +max 38 ssa38
====================
========prog========
-------block------
st_col 46 new
  add 42 reg0
    add 29 ssa29
      const 0 ssa0
      mul 26 ssa26
        const 1 ssa1
        exp2 25 ssa25
          mul 24 ssa24
            log2 23 ssa23
              max 22 ssa22
                add 21 ssa21
                  add 19 ssa19
                    mul 17 ssa17
                      mul 14 ssa14
                        ld_var 7 ssa7
                        rsqrt 13 ssa13
                          add 12 ssa12
                            add 10 ssa10
                              mul 8 ssa8
                                ld_var 7 ssa7
                              mul 9 ssa9
                                ld_var 7 ssa7
                            mul 11 ssa11
                              ld_var 7 ssa7
                      const 2 ssa2
                    mul 18 ssa18
                      mul 15 ssa15
                        ld_var 7 ssa7
                        +rsqrt 13 ssa13
                      const 2 ssa2
                  mul 20 ssa20
                    mul 16 ssa16
                      ld_var 7 ssa7
                      +rsqrt 13 ssa13
                    const 2 ssa2
                const 3 ssa3
            const 4 ssa4
    mul 39 ssa39
      const 5 ssa5
      max 38 ssa38
        add 37 ssa37
          add 35 ssa35
            mul 33 ssa33
              +mul 14 ssa14
              const 6 ssa6
            mul 34 ssa34
              +mul 15 ssa15
              const 6 ssa6
          mul 36 ssa36
            +mul 16 ssa16
            const 6 ssa6
        const 3 ssa3
  add 43 reg0
    add 30 ssa30
      const 0 ssa0
      mul 27 ssa27
        const 1 ssa1
        +exp2 25 ssa25
    mul 40 ssa40
      const 5 ssa5
      +max 38 ssa38
  add 44 reg0
    add 31 ssa31
      const 0 ssa0
      mul 28 ssa28
        const 1 ssa1
        +exp2 25 ssa25
    mul 41 ssa41
      const 5 ssa5
      +max 38 ssa38
  add 45 reg0
    add 32 ssa32
      const 0 ssa0
      +exp2 25 ssa25
    +max 38 ssa38
====================
ppir: node_to_instr create move 47 from store 46
ppir: node_to_instr duplicate const 48 from 1
ppir: node_to_instr duplicate const 49 from 1
ppir: node_to_instr duplicate const 50 from 5
ppir: node_to_instr duplicate const 51 from 5
ppir: node_to_instr duplicate const 52 from 0
ppir: node_to_instr duplicate const 53 from 0
ppir: node_to_instr duplicate const 54 from 0
ppir: node_to_instr duplicate const 55 from 2
ppir: node_to_instr duplicate const 56 from 2
ppir: node_to_instr duplicate const 57 from 6
ppir: node_to_instr duplicate const 58 from 6
ppir: node_to_instr duplicate const 59 from 3
======ppir instr list======
      vary texl unif vmul smul vadd sadd comb stor const0|1
*000: null null null null null 47   null null null |
 001: null null null null null null 42   null null |
 002: null null null null null null 29   null null 0.100000 1.000000 |
 003: null null null null 26   null null null null 0.160000 1.000000 |
 004: null null null null 39   null null null null 0.800000 1.000000 |
 005: null null null null null null 43   null null |
 006: null null null null null null 30   null null 0.100000 1.000000 |
 007: null null null null 27   null null null null 0.160000 1.000000 |
 008: null null null null 40   null null null null 0.800000 1.000000 |
 009: null null null null null null 44   null null |
 010: null null null null null null 31   null null 0.100000 1.000000 |
 011: null null null null 28   null null null null 0.160000 1.000000 |
 012: null null null null 41   null null null null 0.800000 1.000000 |
 013: null null null null null null 45   null null |
 014: null null null null null null 32   null null 0.100000 1.000000 |
 015: null null null null null null null 25   null |
 016: null null null null 24   null null null null 100.000000 |
 017: null null null null null null null 23   null |
 018: null null null null null null 22   null null 0.000000 |
 019: null null null null null null 21   null null |
 020: null null null null 17   null 19   null null 0.408248 0.816497 |
 021: null null null null 18   null null null null 0.408248 0.816497 |
 022: null null null null 20   null null null null 0.408248 0.816497 |
 023: null null null null null null 38   null null 0.000000 |
 024: null null null null null null 37   null null |
 025: null null null null 33   null 35   null null 0.666667 0.333333 |
 026: null null null null 14   null null null null |
 027: null null null null 34   null null null null 0.666667 0.333333 |
 028: null null null null 15   null null null null |
 029: null null null null 36   null null null null 0.666667 0.333333 |
 030: null null null null 16   null null null null |
 031: null null null null null null null 13   null |
 032: null null null null null null 12   null null |
 033: null null null null 8    null 10   null null |
 034: null null null null 9    null null null null |
 035: null null null null 11   null null null null |
 036: 7    null null null null null null null null |
------------------------
======ppir instr depend======
[0[1[2[3[15[16[17[18[19[20[26[36][31[32[33[36][34[36]]][35[36]]]]][21[28[36][+31]]]][22[30[36][+31]]]]]]]]]][4[23[24[25[+26][27[+28]]][29[+30]]]]]][5[6[7[+15]]][8[+23]]][9[10[11[+15]]][12[+23]]][13[14[+15]][+23]]]
------------------------
==14759== Use of uninitialised value of size 8
==14759==    at 0x573AD40: ra_add_node_adjacency (register_allocate.c:402)
==14759==    by 0x573B5E7: ra_add_node_interference (register_allocate.c:467)
==14759==    by 0x58CF76B: ppir_regalloc_prog (regalloc.c:342)
==14759==    by 0x58CCCCB: ppir_compile_nir (nir.c:482)
==14759==    by 0x58C3BE7: lima_create_fs_state (lima_program.c:186)
==14759==    by 0x5697833: st_create_fp_variant (st_program.c:1103)
==14759==    by 0x5698EAB: st_get_fp_variant (st_program.c:1251)
==14759==    by 0x56592D7: st_update_fp (st_atom_shader.c:141)
==14759==    by 0x56563EB: st_validate_state (st_atom.c:262)
==14759==    by 0x5670C0B: prepare_draw (st_draw.c:123)
==14759==    by 0x5670C0B: st_draw_vbo (st_draw.c:153)
==14759==    by 0x563B51F: vbo_draw_arrays (vbo_exec_array.c:391)
==14759==    by 0x1820B7: Mesh::render_vbo() (mesh.cpp:583)
==14759==
==14759== Invalid read of size 8
==14759==    at 0x573AD40: ra_add_node_adjacency (register_allocate.c:402)
==14759==    by 0x573B5E7: ra_add_node_interference (register_allocate.c:467)
==14759==    by 0x58CF76B: ppir_regalloc_prog (regalloc.c:342)
==14759==    by 0x58CCCCB: ppir_compile_nir (nir.c:482)
==14759==    by 0x58C3BE7: lima_create_fs_state (lima_program.c:186)
==14759==    by 0x5697833: st_create_fp_variant (st_program.c:1103)
==14759==    by 0x5698EAB: st_get_fp_variant (st_program.c:1251)
==14759==    by 0x56592D7: st_update_fp (st_atom_shader.c:141)
==14759==    by 0x56563EB: st_validate_state (st_atom.c:262)
==14759==    by 0x5670C0B: prepare_draw (st_draw.c:123)
==14759==    by 0x5670C0B: st_draw_vbo (st_draw.c:153)
==14759==    by 0x563B51F: vbo_draw_arrays (vbo_exec_array.c:391)
==14759==    by 0x1820B7: Mesh::render_vbo() (mesh.cpp:583)
==14759==  Address 0x10 is not stack'd, malloc'd or (recently) free'd
==14759==
==14759==
==14759== Process terminating with default action of signal 11 (SIGSEGV): dumping core
==14759==  Access not within mapped region at address 0x10
==14759==    at 0x573AD40: ra_add_node_adjacency (register_allocate.c:402)
==14759==    by 0x573B5E7: ra_add_node_interference (register_allocate.c:467)
==14759==    by 0x58CF76B: ppir_regalloc_prog (regalloc.c:342)
==14759==    by 0x58CCCCB: ppir_compile_nir (nir.c:482)
==14759==    by 0x58C3BE7: lima_create_fs_state (lima_program.c:186)
==14759==    by 0x5697833: st_create_fp_variant (st_program.c:1103)
==14759==    by 0x5698EAB: st_get_fp_variant (st_program.c:1251)
==14759==    by 0x56592D7: st_update_fp (st_atom_shader.c:141)
==14759==    by 0x56563EB: st_validate_state (st_atom.c:262)
==14759==    by 0x5670C0B: prepare_draw (st_draw.c:123)
==14759==    by 0x5670C0B: st_draw_vbo (st_draw.c:153)
==14759==    by 0x563B51F: vbo_draw_arrays (vbo_exec_array.c:391)
==14759==    by 0x1820B7: Mesh::render_vbo() (mesh.cpp:583)
==14759==  If you believe this happened as a result of a stack
==14759==  overflow in your program's main thread (unlikely but
==14759==  possible), you can try to increase the size of the
==14759==  main thread stack using the --main-stacksize= flag.
==14759==  The main thread stack size used in this run was 8388608.