display7seg

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-- Company:         UTCN
-- Engineer:
--
-- Create Date:     02/04/2016 10:12:56 AM
-- Design Name:     displ7seg
-- Module Name:     displ7seg - Behavioral
-- Project Name:
-- Target Devices:  Nexys4 DDR (xc7a100tcsg324-1)
-- Tool Versions:   Vivado 2015.4, Vivado 2016.4
-- Description:     Multiplexor pentru afisajul cu 7 segmente
--                  Datele de la intrare se interpreteaza ca valori hexazecimale
--                  si sunt decodificate in configuratia segmentelor afisajului
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

entity display7seg is
    Port ( Clk  : in  STD_LOGIC;
           Rst  : in  STD_LOGIC;
           Data : in  STD_LOGIC_VECTOR (7 downto 0);   -- datele pentru 8 cifre (cifra 1 din stanga: biti 31..28)
           An   : out STD_LOGIC_VECTOR (7 downto 0);    -- selectia anodului activ
           Seg  : out STD_LOGIC_VECTOR (7 downto 0));   -- selectia catozilor (segmentelor) cifrei active
end display7seg;

architecture Behavioral of display7seg is
begin
    An<="11111110";
decoder: entity work.scancodeTochar
    port map(scancode=>Data,char=>Seg);
end Behavioral;