Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- USE ieee.std_logic_arith.all;
- entity koder is
- port(
- clk : in STD_LOGIC;
- din : in std_logic);
- end koder;
- architecture Behavioral of koder is
- signal dout: std_logic;
- type rom is array (0 to 2) of std_logic;
- signal soderzhimoe : rom := (others=> '0');
- ----------------------------------------------------------------------------
- begin
- process(clk) begin
- if rising_edge(clk) then
- soderzhimoe(1) <= soderzhimoe(0);
- soderzhimoe(0) <= din xor (soderzhimoe(1) xor soderzhimoe(2));
- soderzhimoe(2) <= soderzhimoe(1);
- dout <= soderzhimoe(0) xor soderzhimoe(2);
- end if;
- end process;
- end behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement