--------------------------------------------------
--- A slice of addition: two bit add
--- Initial 2-bit add that produces a sum and carry
--------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;

ENTITY famakin_first_slice IS
PORT (
    OP_A :IN STD_LOGIC;
    OP_B :IN STD_LOGIC;
    SUM_Q :OUT STD_LOGIC;
    CARRY_Q :OUT STD_LOGIC
 );
END famakin_first_slice;

ARCHITECTURE arch OF famakin_first_slice IS
CONSTANT OP_C: STD_LOGIC:='0';
BEGIN
SUM_Q <= OP_A XOR OP_B XOR OP_C;
CARRY_Q <= ((OP_A XOR OP_B) AND OP_C) OR (OP_A AND OP_B);
END arch;


--------------------------------------------------
--- A slice of addition: three bit add
--- Subsequent additions that use the carry of
--- previous additions to produce a new sum and
--- carry
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity famakin_fa_slice is
port (
      OP_A: in std_logic;
      OP_B: in std_logic;
      OP_C: in std_logic; ---this is the carry from the previous slice
      SUM_Q: out std_logic;
      CARRY_Q: out std_logic
    );
end famakin_fa_slice;

architecture arch of famakin_fa_slice is
begin
     SUM_Q <= OP_A xor OP_B xor OP_C;
     CARRY_Q <= ((OP_A xor OP_B) and OP_C) or (OP_A and OP_B);
end arch;

--------------------------------------------------------
---- Interslice register that holds the sum and carry
---- from a stage for one clock cycle and
---- also passes the sum, carry and MSBs over to the next
---- 4-bit stage addition.
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity reg_fa is
 generic (P: integer:=16;
      W: integer:=4;
      E: integer:=8
        );
 port (CLK: in std_logic;
       Reset: in std_logic;
       EN: in std_logic;
       OP_A: in std_logic_vector(P-1 downto 0);
       OP_B: in std_logic_vector(P-1 downto 0);
       OP_SUM: in std_logic_vector(W-1 downto 0);
       OP_CARRY: in std_logic;
       OP_AQ: out std_logic_vector(P-1 downto 0);
       OP_BQ: out std_logic_vector(P-1 downto 0);
       OP_SQ: out std_logic_vector(W-1 downto 0);
       OP_C: out std_logic
     );
end reg_fa;

architecture arch of reg_fa is
signal DA: std_logic_vector(P-1 downto 0);
signal DB: std_logic_vector(P-1 downto 0);
signal DS: std_logic_vector(W-1 downto 0);
signal DC: std_logic;

begin
   p_reg_fa: process(CLK)
begin
    if (CLK'event and CLK='1') then

       if(Reset='1') then
          DA <= (others => '0');
          DB <= (others => '0');
      DS <= (others => '0');
      DC <= '0';
       elsif (EN='1') then
      DA <= OP_A;
          DB <= OP_B;
      DS <= OP_SUM;
      DC <= OP_CARRY;
       else
      DA <= DA;
          DB <= DB;
      DS <= DS;
      DC <= DC;
       end if;
    end if;
end process p_reg_fa;

OP_AQ <= DA;
OP_BQ <= DB;
OP_SQ <= DS;
OP_C <= DC;

end arch;

-------------------------------------------
----- last slice register for the 4-stage
----- full adder that spits out the final
----- sum and the flag
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity reg_fa_lastslice is
 generic (P: integer:= 16;
      W: integer:= 4;
      E: integer:= 8
        );
 port (CLK: in std_logic;
       Reset: in std_logic;
       EN: in std_logic;
       OP_A: in std_logic; --sign bit
       OP_B: in std_logic; --sign bit--
       OP_SUM: in std_logic_vector(P-1 downto 0);
       OP_CARRY: in std_logic;
       OP_Q: out std_logic_vector(P-1 downto 0);
       OP_F: out std_logic_vector(W-2 downto 0)
    );
end reg_fa_lastslice;

architecture arch of reg_fa_lastslice is
signal DS: std_logic_vector(P-1 downto 0);
signal DC: std_logic_vector(W-2 downto 0);

begin
  p_reg_fa: process(CLK)
begin
    if (CLK'event and CLK='1') then

       if (Reset = '1') then
           DS <= (others => '0');
       DC <= (others => '0');
       elsif (EN= '1') then
       DS <= OP_SUM;
       DC <= OP_A & OP_B & OP_CARRY;
       else
       DS <= DS;
       DC <= DC;
       end if;
    end if;
end process p_reg_fa;
OP_Q <= DS;
OP_F <= DC;

end arch;