module conv2d
(
    input logic CLK,
    input logic RESET,
    input logic [31:0] inputVol [48:0],
    input logic [31:0] convKernel [8:0],
    input logic stride,
    output logic [31:0] outputVol [8:0]
);


logic [31:0] patch1 [8:0];
logic [31:0] patch2 [8:0];
logic [31:0] patch3 [8:0];
logic [31:0] patch4 [8:0];
logic [31:0] patch5 [8:0];
logic [31:0] patch6 [8:0];
logic [31:0] patch7 [8:0];
logic [31:0] patch8 [8:0];
logic [31:0] patch9 [8:0];

assign patch1[0] = inputVol[0];
assign patch1[1] = inputVol[1];
assign patch1[2] = inputVol[2];
assign patch1[3] = inputVol[7];
assign patch1[4] = inputVol[8];
assign patch1[5] = inputVol[9];
assign patch1[6] = inputVol[14];
assign patch1[7] = inputVol[15];
assign patch1[8] = inputVol[16];



assign patch2[0] = inputVol[2];
assign patch2[1] = inputVol[3];
assign patch2[2] = inputVol[4];
assign patch2[3] = inputVol[9];
assign patch2[4] = inputVol[10];
assign patch2[5] = inputVol[11];
assign patch2[6] = inputVol[16];
assign patch2[7] = inputVol[17];
assign patch2[8] = inputVol[18];




assign patch3[0] = inputVol[4];
assign patch3[1] = inputVol[5];
assign patch3[2] = inputVol[6];
assign patch3[3] = inputVol[11];
assign patch3[4] = inputVol[12];
assign patch3[5] = inputVol[13];
assign patch3[6] = inputVol[18];
assign patch3[7] = inputVol[19];
assign patch3[8] = inputVol[20];



assign patch4[0] = inputVol[14];
assign patch4[1] = inputVol[15];
assign patch4[2] = inputVol[16];
assign patch4[3] = inputVol[21];
assign patch4[4] = inputVol[22];
assign patch4[5] = inputVol[23];
assign patch4[6] = inputVol[28];
assign patch4[7] = inputVol[29];
assign patch4[8] = inputVol[30];




assign patch5[0] = inputVol[16];
assign patch5[1] = inputVol[17];
assign patch5[2] = inputVol[18];
assign patch5[3] = inputVol[23];
assign patch5[4] = inputVol[24];
assign patch5[5] = inputVol[25];
assign patch5[6] = inputVol[30];
assign patch5[7] = inputVol[31];
assign patch5[8] = inputVol[32];



assign patch6[0] = inputVol[18];
assign patch6[1] = inputVol[19];
assign patch6[2] = inputVol[20];
assign patch6[3] = inputVol[25];
assign patch6[4] = inputVol[26];
assign patch6[5] = inputVol[27];
assign patch6[6] = inputVol[32];
assign patch6[7] = inputVol[33];
assign patch6[8] = inputVol[34];


assign patch7[0] = inputVol[28];
assign patch7[1] = inputVol[29];
assign patch7[2] = inputVol[30];
assign patch7[3] = inputVol[35];
assign patch7[4] = inputVol[36];
assign patch7[5] = inputVol[37];
assign patch7[6] = inputVol[42];
assign patch7[7] = inputVol[43];
assign patch7[8] = inputVol[44];


assign patch8[0] = inputVol[30];
assign patch8[1] = inputVol[31];
assign patch8[2] = inputVol[32];
assign patch8[3] = inputVol[37];
assign patch8[4] = inputVol[38];
assign patch8[5] = inputVol[39];
assign patch8[6] = inputVol[44];
assign patch8[7] = inputVol[45];
assign patch8[8] = inputVol[46];


assign patch9[0] = inputVol[32];
assign patch9[1] = inputVol[33];
assign patch9[2] = inputVol[34];
assign patch9[3] = inputVol[39];
assign patch9[4] = inputVol[40];
assign patch9[5] = inputVol[41];
assign patch9[6] = inputVol[46];
assign patch9[7] = inputVol[47];
assign patch9[8] = inputVol[48];



logic [31:0] sum1;
logic [31:0] sum2;
logic [31:0] sum3;
logic [31:0] sum4;
logic [31:0] sum5;
logic [31:0] sum6;
logic [31:0] sum7;
logic [31:0] sum8;
logic [31:0] sum9;


mat_mul_accl Mult1(.CLK, .RESET, .mat1(patch1),
                .mat2(convKernel), .SUM(sum1));
mat_mul_accl Mult2(.CLK, .RESET, .mat1(patch2),
                .mat2(convKernel), .SUM(sum2));
mat_mul_accl Mult3(.CLK, .RESET, .mat1(patch3),
                .mat2(convKernel), .SUM(sum3));
mat_mul_accl Mult4(.CLK, .RESET, .mat1(patch4),
                .mat2(convKernel), .SUM(sum4));
mat_mul_accl Mult5(.CLK, .RESET, .mat1(patch5),
                .mat2(convKernel), .SUM(sum5));
mat_mul_accl Mult6(.CLK, .RESET, .mat1(patch6),
                .mat2(convKernel), .SUM(sum6));
mat_mul_accl Mult7(.CLK, .RESET, .mat1(patch7),
                .mat2(convKernel), .SUM(sum7));
mat_mul_accl Mult8(.CLK, .RESET, .mat1(patch8),
                .mat2(convKernel), .SUM(sum8));
mat_mul_accl Mult9(.CLK, .RESET, .mat1(patch9),
                .mat2(convKernel), .SUM(sum9));


assign outputVol[0] = sum1;
assign outputVol[1] = sum2;
assign outputVol[2] = sum3;
assign outputVol[3] = sum4;
assign outputVol[4] = sum5;
assign outputVol[5] = sum6;
assign outputVol[6] = sum7;
assign outputVol[7] = sum8;
assign outputVol[8] = sum9;



endmodule