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VGV952CJW33-E-IR.dts

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Feb 26th, 2019
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  1. /dts-v1/;
  2.  
  3. #include "vr9.dtsi"
  4.  
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/mips/lantiq_rcu_gphy.h>
  7.  
  8. / {
  9. model = "EasyBox 904 xDSL";
  10. compatible = "lantiq,vgv952cjw33-e-ir", "lantiq,xway", "lantiq,vr9";
  11.  
  12. chosen {
  13. // No vpe, both cores used for linux:
  14.  
  15. //Rootfs is in partition 'ubi' if present, volume 'rootfs' (1st search prio). Or in mtd partition called 'rootfs' (2nd prio).
  16. bootargs = "console=ttyLTQ0,115200";
  17.  
  18. // Obsolete:
  19. // bootargs = "console=ttyLTQ0,115200 ubi.mtd=12,2048 panic=1 DTS-TEST-SEQNO=77 root=/dev/ubiblock0_0 rootdelay=7";
  20.  
  21.  
  22. // With vpe, one core dedicated to phone audio signal processing
  23.  
  24. // bootargs = "console=ttyLTQ0,115200 mem=116M phym=128M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp";
  25.  
  26. // Bootargs to boot from sda1
  27. // bootargs = "console=ttyLTQ0,115200 root=/dev/sda1 rootdelay=7 rootfstype=f2fs mem=116M phym=128M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp";
  28.  
  29. // Obsolete:
  30. // bootargs = "console=ttyLTQ0,115200 ubi.mtd=12,2048 panic=1 DTS-TEST-SEQNO=77 root=/dev/ubiblock0_0 rootdelay=7 mem=116M phym=128M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp";
  31. // Bootargs to boot from mtd12 ubifs
  32. // bootargs = "console=ttyLTQ0,115200 ubi.mtd=12,2048 panic=1 DTS-TEST-SEQNO=77 root=/dev/ubiblock0_0 rootdelay=7 mem=116M phym=128M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp";
  33. // bootargs = "console=ttyLTQ0,115200 ubi.mtd=12,2048 panic=1 DTS-TEST-SEQNO=77 root=/dev/ubiblock0_0 rootdelay=7 mem=116M phym=128M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp";
  34. // bootargs = "console=ttyLTQ0,115200 mem=116M phym=128M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp";
  35. // Bootargs to boot from sda1
  36. // bootargs = "console=ttyLTQ0,115200 panic=1 DTS-TEST-SEQNO=77 root=/dev/sda1 rootdelay=7 rootfstype=f2fs mem=116M phym=128M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp";
  37. };
  38.  
  39. memory@0 {
  40. reg = <0x0 0x8000000>;
  41. };
  42.  
  43. gpio-keys-polled {
  44. compatible = "gpio-keys-polled";
  45. #address-cells = <1>;
  46. #size-cells = <0>;
  47. poll-interval = <100>;
  48. rfkill {
  49. label = "wps";
  50. gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
  51. linux,code = <KEY_WPS_BUTTON>;
  52. };
  53. reset {
  54. label = "reset";
  55. gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
  56. linux,code = <KEY_RESTART>;
  57. };
  58. };
  59.  
  60. usb_vbus: regulator-usb-vbus {
  61. compatible = "regulator-fixed";
  62.  
  63. regulator-name = "USB_VBUS";
  64.  
  65. regulator-min-microvolt = <5000000>;
  66. regulator-max-microvolt = <5000000>;
  67.  
  68. gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
  69. enable-active-high;
  70. };
  71.  
  72. gpio-leds {
  73. compatible = "gpio-leds";
  74.  
  75. power_green: power {
  76. label = "VGV952CJW33:red:power";
  77. gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;
  78. default-state = "keep";
  79. };
  80. };
  81.  
  82. spi {
  83. compatible = "spi-gpio";
  84. address-cells = <1>;
  85. size-cells = <0>;
  86.  
  87. gpio-sck = <&gpio 29 GPIO_ACTIVE_HIGH >;
  88. gpio-mosi = <&gpio 30 GPIO_ACTIVE_HIGH >;
  89. num-chipselects = <1>;
  90. cs-gpios = <&gpio 39 GPIO_ACTIVE_HIGH >;
  91.  
  92. hc595: gpio_spi@0 {
  93. compatible = "fairchild,74hc595";
  94. reg = <0>;
  95. registers-number = <1>;
  96. spi-max-frequency = <1000000>;
  97. spi-cpol = <0>;
  98. spi-cpha = <0>;
  99. gpio-controller;
  100. #gpio-cells = <2>;
  101. };
  102. };
  103.  
  104. gpio_export {
  105. compatible = "gpio-export";
  106. #size-cells = <0>;
  107.  
  108. out_0 { /*Unknown*/
  109. gpio-export,name = "hc595_0";
  110. gpio-export,output = <1>;
  111. gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
  112. };
  113. out_1 {/*Unknown*/
  114. gpio-export,name = "hc595_1";
  115. gpio-export,output = <1>;
  116. gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
  117. };
  118.  
  119. // out_2 is used to reset touch IC and owned by eb904_keypad
  120.  
  121. out_3 {/*Unknown*/
  122. gpio-export,name = "hc595_3";
  123. gpio-export,output = <1>;
  124. gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
  125. };
  126. out_dsl_eth { /* Switches DSL line + 100MiB eth or 1GiB ethernet on DSL/WAN input. Relay 1.*/
  127. gpio-export,name = "dsl_en";
  128. gpio-export,output = <1>;
  129. gpios = <&hc595 4 GPIO_ACTIVE_LOW>;
  130. };
  131. out_5 { /* Switches filter for DSL line On/Off. Relays 2 and 3 simultaneously.*/
  132. gpio-export,name = "annexj";
  133. gpio-export,output = <1>;
  134. gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
  135. };
  136. out_6 { /* Switch DSL line betwean ISDN modem and Si3050. Relay 5.*/
  137. gpio-export,name = "annexb";
  138. gpio-export,output = <1>;
  139. gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
  140. };
  141. out_7 { /* Switch phone outputs N and F betwean analog DSL line and XS1 output from Lantiq SLIC. Relay 4.*/
  142. gpio-export,name = "annexa";
  143. gpio-export,output = <1>;
  144. gpios = <&hc595 7 GPIO_ACTIVE_LOW>;
  145. };
  146. };
  147.  
  148. i2c {
  149. compatible = "i2c-gpio";
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. gpios = <&gpio 19 GPIO_ACTIVE_HIGH /* sda */
  153. &gpio 14 GPIO_ACTIVE_HIGH /* scl */
  154. >;
  155. //i2c-gpio,sda-open-drain;
  156. //i2c-gpio,scl-open-drain;
  157. i2c-gpio,delay-us = <5>;
  158. /* Add touch panel Support */
  159. tp: eb904tp@0x14 {
  160. compatible = "lantiq,eb904_keypad";
  161. reg = <0x14>;
  162. interrupt-parent = <&icu0>;
  163. interrupts = <135>;
  164. eb904,interrupt-gpio = <&gpio 0 GPIO_ACTIVE_HIGH /* EXIN */>;
  165. eb904,ctrl-rst-gpio = <&hc595 2 GPIO_ACTIVE_LOW /* rst */>;
  166. eb904,alphas = /bits/ 8
  167. <0x07 /* left */
  168. 0x0a /* down */
  169. 0x0a /* right */
  170. 0x0a /* ok */
  171. 0x07 /* up */
  172. >;
  173. keypad,num-rows = <3>;
  174. keypad,num-columns = <3>;
  175. linux,keymap = <
  176. MATRIX_KEY(0x0, 0x1, KEY_UP) /* ROW0, COL1 */
  177. MATRIX_KEY(0x1, 0x0, KEY_LEFT) /* ROW1, COL0 */
  178. MATRIX_KEY(0x1, 0x1, KEY_ENTER) /* ROW1, COL1 */
  179. MATRIX_KEY(0x1, 0x2, KEY_RIGHT) /* ROW1, COL2 */
  180. MATRIX_KEY(0x2, 0x1, KEY_DOWN) /* ROW2, COL1 */
  181. >;
  182. };
  183. };
  184.  
  185. mdio: mdio {
  186. compatible = "lantiq,xrx200-mdio";
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. phy0: ethernet-phy@0 {
  190. reg = <0x0>;
  191. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  192. };
  193. phy1: ethernet-phy@1 {
  194. reg = <0x1>;
  195. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  196. };
  197. /*
  198. phy5: ethernet-phy@5 {
  199. reg = <0x5>;
  200. };
  201. */
  202. phy11: ethernet-phy@11 {
  203. reg = <0x11>;
  204. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  205. };
  206. phy12: ethernet-phy@12 {
  207. reg = <0x12>;
  208. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  209. };
  210. phy13: ethernet-phy@13 {
  211. reg = <0x13>;
  212. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  213. };
  214. phy14: ethernet-phy@14 {
  215. reg = <0x14>;
  216. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  217. };
  218. };
  219.  
  220. rtl8367b {
  221. compatible = "realtek,rtl8367b";
  222. //gpio-sda = <&gpio0 1 0>;
  223. //gpio-sck = <&gpio0 2 0>;
  224. //cpu_port = <7>;
  225. //realtek,extif0 = <1 0 1 1 1 1 1 1 2>; // default found on other profiles
  226. realtek,extif1 = <1 0 1 1 0 0 1 1 2>; // based on vendor uboot-config
  227. mii-bus = <&mdio>;
  228. };
  229. };
  230.  
  231. &vmmc {
  232. status = "okay";
  233. gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; //reset_slic!
  234. };
  235.  
  236. &localbus {
  237. // #address-cells = <2>; // Just for info. From vr9.dtsi
  238. // #size-cells = <1>;
  239. // ranges = <0 0 0x0 0x3ffffff // addrsel0 0x3ffffff and 0x4000010 in vr9.dtsi seem to be wrong, because these are size
  240. // 1 0 0x4000000 0x4000010>; // addrsel1 parameters. Not really a problem; the drivers we have use their own hardcoded values
  241.  
  242. ranges = <0 0 0x0 0x2000000 // addrsel0 Was set up this way by arcadian eb904 U-Boot for nand. Not used by eb904 linux
  243. 1 0 0x2000000 0x1000000 // addrsel1 Size 0x1000000 hardcoded in xway_nand.c. Excessive, as first 0x80 is used only
  244. 2 0 0x3000000 0x0000800>; // addrsel2 Size 0x800 hardcoded in display driver. This is the min size supported by ebu
  245.  
  246. nand@1 { // @1 because using ebu BUSCON1/ADDSEL1
  247. compatible = "lantiq,nand-xway";
  248. reg = <1 0x0 0x80>; // Only adresses 0x0..0x7F needed (but driver ignores size 0x80 and tells ebu to map 0x1000000)
  249.  
  250. // bank-width = <2>; // Not used by any driver code
  251. #address-cells = <1>;
  252. #size-cells = <1>;
  253. lantiq,cs = <1>; // Seems to be needed (EASY80920NAND.dts)
  254.  
  255. nand-on-flash-bbt;
  256. customized-samsung-K9F4G08U0x;
  257.  
  258. partitions {
  259. compatible = "fixed-partitions";
  260. #address-cells = <1>;
  261. #size-cells = <1>;
  262.  
  263. partition@0 {
  264. label = "uboot";
  265. reg = <0x0 0x40000>;
  266. };
  267.  
  268. partition@40000 {
  269. label = "rootfs1"; // Called "rootfs" in original u-boot env.
  270. reg = <0x40000 0x3C00000>; // Auto mounted as rootfs if no UBI volume named "rootfs" exists
  271. };
  272.  
  273. partition@3C40000 {
  274. label = "kernel"; // Called "kernel" in original u-boot env.
  275. reg = <0x3C40000 0x500000>;
  276. };
  277.  
  278. partition@4140000 {
  279. label = "tmp1";
  280. reg = <0x4140000 0x100000>;
  281. };
  282.  
  283. partition@4240000 {
  284. label = "tmp2";
  285. reg = <0x4240000 0x200000>;
  286. };
  287.  
  288. partition@4440000 {
  289. label = "sysconfig";
  290. reg = <0x4440000 0x100000>;
  291. };
  292.  
  293. partition@4540000 {
  294. label = "ubootconfig";
  295. reg = <0x4540000 0x100000>;
  296. };
  297.  
  298. partition@4640000 {
  299. label = "fwdiag";
  300. reg = <0x4640000 0xC0000>;
  301. };
  302.  
  303. partition@4700000 {
  304. label = "lcdimage";
  305. reg = <0x4700000 0x300000>;
  306. };
  307.  
  308. partition@4A00000 {
  309. label = "mfgconfig";
  310. reg = <0x4A00000 0x100000>;
  311. };
  312.  
  313. partition@4B00000 {
  314. label = "sipdata";
  315. reg = <0x4B00000 0x100000>;
  316. };
  317.  
  318. partition@4C00000 {
  319. label = "voice";
  320. reg = <0x4C00000 0x4000000>;
  321. };
  322.  
  323. partition@8C00000 { // Called "misc" in original u-boot env.
  324. label = "ubi"; // Rename to "ubi" for auto ubi attachment and usage of rootfs, rootfs_data, kernel volumes
  325. reg = <0x8C00000 0x13200000>; // Rename to "firmware" for special squashfs-rootfs/jffs2-rootfs_data treatment
  326. };
  327.  
  328. partition@1BE00000 {
  329. label = "rootfs2";
  330. reg = <0x1BE00000 0x3c00000>;
  331. };
  332.  
  333. partition@1FA00000 {
  334. label = "kernel2";
  335. reg = <0x1FA00000 0x500000>;
  336. };
  337.  
  338. partition@1FF00000 {
  339. label = "mystery"; // Missing in original u-boot environment, seems to be empty (erased)
  340. reg = <0x1FF00000 0x100000>;
  341. };
  342. };
  343. };
  344.  
  345. display@2 { // @2 because using ebu BUSCON2/ADDSEL2. Name not 'easybox904-display',
  346. compatible = "ilitek,ili9341_eb904"; // see 'Node Names' at https://elinux.org/Device_Tree_Usage
  347. reg = <2 0x0 0x4>; // Size 0x4 contains 2 byte data and 2 byte command registers
  348. status = "okay";
  349. rotate = <270>;
  350. fps = <30>;
  351. bgr;
  352. buswidth = <8>;
  353. reset-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
  354. led-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
  355. debug = <1>;
  356. };
  357. };
  358.  
  359. /*
  360. * Following is the very experimental part which is broken and requires much more elaboration
  361. */
  362.  
  363. // From FRITZ3370.dts
  364. &gpio {
  365. pinctrl-names = "default";
  366. pinctrl-0 = <&state_default>;
  367.  
  368. state_default: pinmux {
  369. mdio {
  370. lantiq,groups = "mdio";
  371. lantiq,function = "mdio";
  372. };
  373.  
  374. phy-rst { // I have no idea wether this makes sense
  375. lantiq,pins = "io37", "io44"; // FRITZ3370.dts
  376. // lantiq,pins = "io42"; // TDW8970.dts
  377. lantiq,pull = <0>;
  378. lantiq,open-drain = <0>;
  379. lantiq,output = <1>;
  380. };
  381.  
  382. pcie-rst {
  383. lantiq,pins = "io38"; // FRITZ3370.dts, TDW8970.dts, EASY80920.dtsi, P2812HNUFX.dtsi
  384. // lantiq,pins = "io21"; // ARV7519RW22.dts
  385. lantiq,pull = <0>;
  386. lantiq,output = <1>;
  387. };
  388.  
  389. exin1 {
  390. lantiq,groups = "exin1";
  391. lantiq,function = "exin";
  392. };
  393.  
  394. conf_tp {
  395. lantiq,pins = "io1"; /* exin1 */
  396. lantiq,open-drain;
  397. lantiq,pull = <0>;
  398. };
  399. conf_spi {
  400. lantiq,pins = "io29", "io30", "io39"; /* gpiois for spi */
  401. lantiq,pull = <2>; /*Pull Up*/
  402. };
  403. };
  404. };
  405.  
  406. &usb_phy0 {
  407. status = "okay";
  408. };
  409.  
  410. &usb_phy1 {
  411. status = "okay";
  412. };
  413.  
  414. &usb0 {
  415. status = "okay";
  416. vbus-supply = <&usb_vbus>;
  417. };
  418.  
  419. &usb1 {
  420. status = "okay";
  421. vbus-supply = <&usb_vbus>;
  422. };
  423.  
  424. &eth0 {
  425. lan: interface@0 {
  426. compatible = "lantiq,xrx200-pdi";
  427. #address-cells = <1>;
  428. #size-cells = <0>;
  429. reg = <0>;
  430. mac-address = [ 00 11 22 33 44 55 ];
  431. lantiq,switch;
  432. ethernet@2 {
  433. compatible = "lantiq,xrx200-pdi-port";
  434. reg = <2>;
  435. phy-mode = "gmii";
  436. // phy-handle = <&phy11>;
  437. fixed-link {
  438. speed = <1000>;
  439. full-duplex;
  440. };
  441. };
  442. /* wan port */
  443. ethernet@4 {
  444. compatible = "lantiq,xrx200-pdi-port";
  445. reg = <4>;
  446. phy-mode = "gmii";
  447. phy-handle = <&phy13>;
  448. };
  449. /* rt3883 soc */
  450. /*
  451. ethernet@5 {
  452. compatible = "lantiq,xrx200-pdi-port";
  453. reg = <5>;
  454. phy-mode = "rgmii";
  455. phy-handle = <&phy5>;
  456. };
  457. */
  458. };
  459. };
  460.  
  461. &pci0 {
  462. status = "disabled";
  463. //gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
  464. };
  465.  
  466. &pcie0 {
  467. pcie@0 {
  468. reg = <0 0 0 0 0>;
  469. #interrupt-cells = <1>;
  470. #size-cells = <2>;
  471. #address-cells = <3>;
  472. device_type = "pci";
  473. };
  474. };
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