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-- Company:
-- Engineer:
--
-- Create Date:    13:45:07 04/10/2010
-- Design Name:
-- Module Name:    downlink - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

library work;
    use work.NG.all;

entity downlink is
    port
    (
        clock              : IN  std_logic;
        reset              : IN  std_logic;

        jpeg_ram_wren      : IN std_logic;
        jpeg_ram_byte      : IN std_logic_vector(7 downto 0);
        jpeg_done          : IN std_logic;

        WLAN1_SSEL          : OUT  std_logic;
        WLAN1_SCK           : OUT  std_logic;
        WLAN1_MOSI          : OUT  std_logic;
        WLAN1_MISO          : IN  std_logic;
        WLAN1_RESET         : OUT  std_logic;

        WLAN2_SSEL          : OUT  std_logic;
        WLAN2_SCK           : OUT  std_logic;
        WLAN2_MOSI          : OUT  std_logic;
        WLAN2_MISO          : IN  std_logic;
        WLAN2_RESET         : OUT  std_logic;

        quality             : OUT std_logic;
        fast                : OUT std_logic;
        channels            : OUT CHANNELS_T;
        channels_available      : OUT std_logic;

        DOWNLINK_RDY            : OUT std_logic;
        DOWNLINK_ALMOST_FULL    : OUT std_logic;

        switches            : IN std_logic_vector(5 downto 0);

        debug               : out std_logic_vector(8 downto 0)

    );
end downlink;

architecture Behavioral of downlink is

    signal device            : std_logic;
    signal WLAN_RDY1         : std_logic;
    signal WLAN_RDY2         : std_logic;
    signal WLAN_ALMOST_FULL1 : std_logic;
    signal WLAN_ALMOST_FULL2 : std_logic;
    signal wlan_done1        : std_logic;
    signal wlan_done2        : std_logic;

    signal payload_available : payload_available_t;

    signal frame_payload_out : frame_payload_t;
    signal frame_payload     : frame_payload_t;
    signal frame_payload_debug : PAYLOAD_T;

    signal wlan_debug1       : std_logic_vector(8 downto 0);
    signal wlan_debug2       : std_logic_vector(8 downto 0);
    signal rc_debug1         : std_logic_vector(8 downto 0);
    signal rc_debug2         : std_logic_vector(8 downto 0);
    signal self_debug        : std_logic_vector(8 downto 0);

    signal jpeg_ram_wren1    : std_logic;
    signal jpeg_ram_byte1    : std_logic_vector(7 downto 0);

    signal jpeg_ram_wren2    : std_logic;
    signal jpeg_ram_byte2    : std_logic_vector(7 downto 0);

    signal payload_debug     : std_logic_vector(8 downto 0);

    signal debug_switches : std_logic_vector(4 downto 0);

    signal jpeg_done_reg : std_logic;

    signal cbc_start, cbc_direction : asl;
    signal cbc_busy, cbc_data_available : asl;
    signal data_in, cbc_crypto_key_in, cbc_cipher_in, cbc_data_in, cbc_auth_key_in, cbc_mac_in : aslv128;
    signal cbc_data_out, cbc_mac_out : std_logic_vector(127 downto 0);

-- unfortunately we can't assign to an array from within different instances, even if there is no contention
-- so we have to introduce dedicated signals and assign them in only one process
    signal channels_available0, quality0, fast0 : std_logic;
    signal channels0 : CHANNELS_T;

    signal channels_available1, quality1, fast1 : std_logic;
    signal channels1 : CHANNELS_T;

    signal cbc_start0, cbc_direction0 : std_logic;
    signal
        cbc_crypto_key_in0,
        cbc_cipher_in0,
        cbc_data_in0,
        cbc_auth_key_in0,
        cbc_mac_in0 : std_logic_vector(127 downto 0);

    signal cbc_start1, cbc_direction1 : std_logic;
    signal
        cbc_crypto_key_in1,
        cbc_cipher_in1,
        cbc_data_in1,
        cbc_auth_key_in1,
        cbc_mac_in1 : std_logic_vector(127 downto 0);

    signal cbc_start2, cbc_direction2 : std_logic;
    signal
        cbc_crypto_key_in2,
        cbc_cipher_in2,
        cbc_data_in2,
        cbc_auth_key_in2,
        cbc_mac_in2 : std_logic_vector(127 downto 0);

    signal cbc_start3, cbc_direction3 : std_logic;
    signal
        cbc_crypto_key_in3,
        cbc_cipher_in3,
        cbc_data_in3,
        cbc_auth_key_in3,
        cbc_mac_in3 : std_logic_vector(127 downto 0);

    signal aes_rc_running : au;

    signal channels_reg : CHANNELS_T;

begin

    Inst_video_stream1: entity work.stream
    generic MAP
    (
    subnet => to_unsigned(0, 8)
    )
    PORT MAP(
        clock => clock,
        reset => reset,

        jpeg_ram_wren => jpeg_ram_wren1,
        jpeg_ram_byte => jpeg_ram_byte1,

        WLAN_SSEL => WLAN1_SSEL,
        WLAN_SCK => WLAN1_SCK,
        WLAN_MOSI => WLAN1_MOSI,
        WLAN_MISO => WLAN1_MISO,
        WLAN_RESET => WLAN1_RESET,

        wlan_rdy => wlan_rdy1,
        wlan_almost_full => wlan_almost_full1,

        frame_payload => frame_payload_out(0),
        data_available => payload_available(0),

        done => wlan_done1,

        cbc_start => cbc_start2,
        cbc_direction_in => cbc_direction2,
        cbc_busy => cbc_busy(2),
        cbc_data_available => cbc_data_available(2),

        cbc_crypto_key_in => cbc_crypto_key_in2,
        cbc_cipher_in => cbc_cipher_in2,
        cbc_data_in => cbc_data_in2,
        cbc_auth_key_in => cbc_auth_key_in2,
        cbc_mac_in => cbc_mac_in2,

        cbc_data_out => cbc_data_out,
        cbc_mac_out => cbc_mac_out,

        switches => switches,
        debug => wlan_debug1
    );

-- DISABLE FOR SIMULATION TO SAVE STATEMENTS
    Inst_video_stream2: entity work.stream
    generic MAP
    (
    subnet => to_unsigned(1, 8)
    )
    PORT MAP(
        clock => clock,
        reset => reset,

        jpeg_ram_wren => jpeg_ram_wren2,
        jpeg_ram_byte => jpeg_ram_byte2,

        WLAN_SSEL => WLAN2_SSEL,
        WLAN_SCK => WLAN2_SCK,
        WLAN_MOSI => WLAN2_MOSI,
        WLAN_MISO => WLAN2_MISO,
        WLAN_RESET => WLAN2_RESET,

        wlan_rdy => wlan_rdy2,
        wlan_almost_full => wlan_almost_full2,

        frame_payload => frame_payload_out(1),
        data_available => payload_available(1),

        done => wlan_done2,

        cbc_start => cbc_start3,
        cbc_direction_in => cbc_direction3,
        cbc_busy => cbc_busy(3),
        cbc_data_available => cbc_data_available(3),

        cbc_crypto_key_in => cbc_crypto_key_in3,
        cbc_cipher_in => cbc_cipher_in3,
        cbc_data_in => cbc_data_in3,
        cbc_auth_key_in => cbc_auth_key_in3,
        cbc_mac_in => cbc_mac_in3,

        cbc_data_out => cbc_data_out,
        cbc_mac_out => cbc_mac_out,

        switches => switches,
        debug => wlan_debug2
    );

    Inst_rc_stream1: entity work.rc_stream
    PORT MAP(
        clock => clock,
        reset => reset,

        frame_payload_out => frame_payload_out(0),
        payload_available => payload_available(0),

        cbc_start => cbc_start0,
        cbc_direction => cbc_direction0,
        cbc_busy => cbc_busy(0),
        cbc_data_available => cbc_data_available(0),

        cbc_crypto_key_in => cbc_crypto_key_in0,
        cbc_cipher_in => cbc_cipher_in0,
        cbc_data_in => cbc_data_in0,
        cbc_auth_key_in => cbc_auth_key_in0,
        cbc_mac_in => cbc_mac_in0,

        cbc_data_out => cbc_data_out,
        cbc_mac_out => cbc_mac_out,

        -- data output
        quality             => quality0,
        fast                => fast0,
        channels            => channels0,
        channels_available  => channels_available0,

        switches => switches,
        debug => rc_debug1
    );

    Inst_rc_stream2: entity work.rc_stream
    PORT MAP(
        clock => clock,
        reset => reset,

        frame_payload_out => frame_payload_out(1),
        payload_available => payload_available(1),

        cbc_start => cbc_start1,
        cbc_direction => cbc_direction1,
        cbc_busy => cbc_busy(1),
        cbc_data_available => cbc_data_available(1),

        cbc_crypto_key_in => cbc_crypto_key_in1,
        cbc_cipher_in => cbc_cipher_in1,
        cbc_data_in => cbc_data_in1,
        cbc_auth_key_in => cbc_auth_key_in1,
        cbc_mac_in => cbc_mac_in1,

        cbc_data_out => cbc_data_out,
        cbc_mac_out => cbc_mac_out,

        -- data output
        quality             => quality1,
        fast                => fast1,
        channels            => channels1,
        channels_available  => channels_available1,

        switches => switches,
        debug => rc_debug2
    );


    Inst_cbc : entity work.cbc
        port map
        (
            clock => clock,
            reset => reset,

            start => cbc_start,
            direction_in => cbc_direction,
            busy_out => cbc_busy,
            data_available => cbc_data_available,

            crypto_key_in => cbc_crypto_key_in,
            cipher_in => cbc_cipher_in,
            data_in => cbc_data_in,
            auth_key_in => cbc_auth_key_in,
            mac_in => cbc_mac_in,

            data_out => cbc_data_out,
            mac_out => cbc_mac_out
        );

    process (
        cbc_start0, cbc_direction0, cbc_crypto_key_in0, cbc_cipher_in0, cbc_data_in0, cbc_auth_key_in0, cbc_mac_in0,
        cbc_start1, cbc_direction1, cbc_crypto_key_in1, cbc_cipher_in1, cbc_data_in1, cbc_auth_key_in1, cbc_mac_in1,
        cbc_start2, cbc_direction2, cbc_crypto_key_in2, cbc_cipher_in2, cbc_data_in2, cbc_auth_key_in2, cbc_mac_in2,
        cbc_start3, cbc_direction3, cbc_crypto_key_in3, cbc_cipher_in3, cbc_data_in3, cbc_auth_key_in3, cbc_mac_in3
    )
    begin
-- unfortunately we can't assign to an array from within different instances, even if there is no contention
-- so we have to introduce dedicated signals and assign them in only one instance
        cbc_start(0) <= cbc_start0;
        cbc_direction(0) <= cbc_direction0;
        cbc_crypto_key_in(0) <= cbc_crypto_key_in0;
        cbc_cipher_in(0) <= cbc_cipher_in0;
        cbc_data_in(0) <= cbc_data_in0;
        cbc_auth_key_in(0) <= cbc_auth_key_in0;
        cbc_mac_in(0) <= cbc_mac_in0;

        cbc_start(1) <= cbc_start1;
        cbc_direction(1) <= cbc_direction1;
        cbc_crypto_key_in(1) <= cbc_crypto_key_in1;
        cbc_cipher_in(1) <= cbc_cipher_in1;
        cbc_data_in(1) <= cbc_data_in1;
        cbc_auth_key_in(1) <= cbc_auth_key_in1;
        cbc_mac_in(1) <= cbc_mac_in1;

        cbc_start(2) <= cbc_start2;
        cbc_direction(2) <= cbc_direction2;
        cbc_crypto_key_in(2) <= cbc_crypto_key_in2;
        cbc_cipher_in(2) <= cbc_cipher_in2;
        cbc_data_in(2) <= cbc_data_in2;
        cbc_auth_key_in(2) <= cbc_auth_key_in2;
        cbc_mac_in(2) <= cbc_mac_in2;

        cbc_start(3) <= cbc_start3;
        cbc_direction(3) <= cbc_direction3;
        cbc_crypto_key_in(3) <= cbc_crypto_key_in3;
        cbc_cipher_in(3) <= cbc_cipher_in3;
        cbc_data_in(3) <= cbc_data_in3;
        cbc_auth_key_in(3) <= cbc_auth_key_in3;
        cbc_mac_in(3) <= cbc_mac_in3;
    end process;

    -- decrypting remote control
    channels <= channels_reg;
    process (clock, reset)
    begin
        if rising_edge(clock) then
            channels_available <= channels_available0 or channels_available1;
            if channels_available0 = '1' then
                channels <= channels0;
                quality <= quality0;
                fast <= fast0;
            elsif channels_available1 = '1' then
                channels <= channels1;
                quality <= quality1;
                fast <= fast1;
            end if;
        end if;

        if reset='1' then
            channels_available <= '0';
            quality <= '0';
            fast <= '0';
            payload_debug <= (others => '0');
        end if;
    end process;

    process (clock, reset)
    begin
        if rising_edge(clock) then

            if wlan_rdy1 = '1' or wlan_rdy2 = '1' then -- both wlans are powered up and configured, activate forever
                downlink_rdy <= '1';
            end if;

            if jpeg_done = '1' then
                device <= not device;
            end if;

            jpeg_ram_wren1 <= '0';
            jpeg_ram_wren2 <= '0';
            if device = '0' then
                downlink_almost_full <= wlan_almost_full1;
                jpeg_ram_wren1 <= jpeg_ram_wren;
                jpeg_ram_byte1 <= jpeg_ram_byte;
                wlan_done1 <= '0';
                wlan_done2 <= '1';
            else
                downlink_almost_full <= wlan_almost_full2;
                jpeg_ram_wren2 <= jpeg_ram_wren;
                jpeg_ram_byte2 <= jpeg_ram_byte;
                wlan_done2 <= '0';
                wlan_done1 <= '1';
            end if;
        end if;

        if reset = '1' then
            device <= '0';
            wlan_done1 <= '0';
            wlan_done2 <= '0';
            jpeg_ram_wren1 <= '0';
            jpeg_ram_wren2 <= '0';
            downlink_rdy <= '0';
            self_debug <= (others => '0');
        end if;
    end process;

    process (clock, reset)
    begin
        if rising_edge(clock) then
-- DISABLE FOR SIMULATION TO SAVE STATEMENTS
            case to_integer(unsigned(switches(0) & switches(1) & switches(2) & switches(3) & switches(4))) is
                when 0 => debug <= '0' & channels_reg(1);
                when 1 => debug <= '0' & channels_reg(2);
                when 2 => debug <= '0' & channels_reg(3);
                when 3 => debug <= '0' & channels_reg(4);
                when 4 => debug <= '0' & channels_reg(5);
                when 5 => debug <= '0' & channels_reg(6);
                when 6 => debug <= '0' & channels_reg(7);
                when 7 => debug <= '0' & channels_reg(8);
                when others => debug <= (others => '0');
            end case;

        end if;
    end process;


end Behavioral;