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MXU macros can replace binutils

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  1. # mxu1_as_macros.s.h
  2. #
  3. # MIPS Ingenic XBurst MXU1 revision 2 SIMD helper macros for GNU GAS
  4. #
  5. # Copyright (c) 2019 Daniel Silsby
  6. #
  7. # Permission is hereby granted, free of charge, to any person
  8. # obtaining a copy of this software and associated documentation
  9. # files (the "Software"), to deal in the Software without restriction,
  10. # including without limitation the rights to use, copy, modify, merge,
  11. # publish, distribute, sublicense, and/or sell copies of the Software,
  12. # and to permit persons to whom the Software is furnished to do so,
  13. # subject to the following conditions:
  14. #
  15. # The above copyright notice and this permission notice shall be included
  16. # in all copies or substantial portions of the Software.
  17. #
  18. # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19. # EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  20. # OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21. # IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
  22. # DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23. # TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  24. # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25.  
  26.  
  27.  
  28. ################################################################################
  29. #  These macros take the place of the unofficial patched Ingenic binutils, and
  30. # the syntax there and here is interchangeable. Users of a toolchain that
  31. # contains that unofficial Ingenic binutils patch should *not* specify '-mmxu'
  32. # on the compiler/assembler command line when using this header.
  33. #
  34. # To include this header in your source do one of the following:
  35. #  1.) In a GAS .S or .s assembly file, add the following at top of file:
  36. #      .include "mxu1_as_macros.s.h"
  37. #  2.) In a GCC C/C++ file using inline asm, add the following at top of file:
  38. #      __asm__ __volatile__(".include \"mxu1_as_macros.s.h\" \n");
  39. #
  40. #  Because of limitations in GAS macro expansion, and the fact that MIPS
  41. # GPR specifiers in GAS do not evaluate to an integer expression, you may run
  42. # into difficulty if you use '.equ' to generically define regs your code uses.
  43. # You cannot, for instance, do this when using this header:
  44. #     .equ R_SRCPTR, $a1
  45. #     lxw  $t0, R_SRCPTR, $t1, 0                # (BROKEN)
  46. # What you *can* do, however, is instead use #define's with the C preprocessor
  47. # for this. This requires your ASM code to be in a .S file (not .s). Example:
  48. #     #define R_SRCPTR $a1
  49. #     lxw  $t0, R_SRCPTR, $t1, 0                # (WORKS)
  50. # An alternative for inline ASM in C/C++ is like so:
  51. #     #define R_SRCPTR "$a1"
  52. #     asm("lxw  $t0, " R_SRCPTR ", $t1, 0 \n"); # (WORKS)
  53. ################################################################################
  54.  
  55.  
  56. .ifndef MXU1_AS_MACROS_S_H
  57. .equ    MXU1_AS_MACROS_S_H, 1
  58.  
  59. # Named MIPS GPR specifiers, i.e. $zero .. $ra
  60. .equiv GPR_$zero, 0
  61. .equiv GPR_$at,   1
  62. .equiv GPR_$v0,   2
  63. .equiv GPR_$v1,   3
  64. .equiv GPR_$a0,   4
  65. .equiv GPR_$a1,   5
  66. .equiv GPR_$a2,   6
  67. .equiv GPR_$a3,   7
  68. .equiv GPR_$t0,   8
  69. .equiv GPR_$t1,   9
  70. .equiv GPR_$t2,   10
  71. .equiv GPR_$t3,   11
  72. .equiv GPR_$t4,   12
  73. .equiv GPR_$t5,   13
  74. .equiv GPR_$t6,   14
  75. .equiv GPR_$t7,   15
  76. .equiv GPR_$s0,   16
  77. .equiv GPR_$s1,   17
  78. .equiv GPR_$s2,   18
  79. .equiv GPR_$s3,   19
  80. .equiv GPR_$s4,   20
  81. .equiv GPR_$s5,   21
  82. .equiv GPR_$s6,   22
  83. .equiv GPR_$s7,   23
  84. .equiv GPR_$t8,   24
  85. .equiv GPR_$t9,   25
  86. .equiv GPR_$k0,   26
  87. .equiv GPR_$k1,   27
  88. .equiv GPR_$gp,   28
  89. .equiv GPR_$sp,   29
  90. .equiv GPR_$fp,   30
  91. .equiv GPR_$s8,   GPR_$fp
  92. .equiv GPR_$ra,   31
  93.  
  94. # Unnamed MIPS GPRs, i.e. $0 .. $31
  95. .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
  96.  .equiv GPR_$\i, \i
  97. .endr
  98.  
  99. # MXU regs xr0 .. xr16
  100. # For use with s32i2m,s32m2i MXU<->GPR reg transfer opcodes (can access xr16)
  101. .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
  102.  .equiv MXU_I2M_M2I_xr\i, \i
  103. .endr
  104.  
  105. # MXU regs xr0 .. xr15
  106. # For use with all other MXU opcodes (4-bit fields can only access xr0..15)
  107. .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
  108.  .equiv MXU_xr\i, \i
  109. .endr
  110.  
  111. # MXU pattern names ptn0 .. ptn7, 0 .. 7
  112. .irp i, 0,1,2,3,4,5,6,7
  113.  .equiv MXU_PTN_ptn\i, \i
  114.  .equiv MXU_PTN_\i, \i
  115. .endr
  116.  
  117. # MXU patterns for 's16mad' opcode (one-channel multiply)
  118. .equiv MXU_MPTN2_HH,    0
  119. .equiv MXU_MPTN2_LL,    1
  120. .equiv MXU_MPTN2_HL,    2
  121. .equiv MXU_MPTN2_LH,    3
  122. .equiv MXU_MPTN2_0,     0
  123. .equiv MXU_MPTN2_1,     1
  124. .equiv MXU_MPTN2_2,     2
  125. .equiv MXU_MPTN2_3,     3
  126.  
  127. # MXU patterns for 's16mad' opcode (one-channel add)
  128. .equiv MXU_APTN1_A,     0
  129. .equiv MXU_APTN1_S,     1
  130. .equiv MXU_APTN1_0,     0
  131. .equiv MXU_APTN1_1,     1
  132.  
  133. # MXU patterns for dual-channel add
  134. .equiv MXU_APTN2_AA,    0
  135. .equiv MXU_APTN2_AS,    1
  136. .equiv MXU_APTN2_SA,    2
  137. .equiv MXU_APTN2_SS,    3
  138. .equiv MXU_APTN2_0,     0
  139. .equiv MXU_APTN2_1,     1
  140. .equiv MXU_APTN2_2,     2
  141. .equiv MXU_APTN2_3,     3
  142.  
  143. # MXU patterns for dual-channel multiply
  144. .equiv MXU_OPTN2_WW,    0
  145. .equiv MXU_OPTN2_LW,    1
  146. .equiv MXU_OPTN2_HW,    2
  147. .equiv MXU_OPTN2_XW,    3
  148. .equiv MXU_OPTN2_0,     0
  149. .equiv MXU_OPTN2_1,     1
  150. .equiv MXU_OPTN2_2,     2
  151. .equiv MXU_OPTN2_3,     3
  152.  
  153.  
  154. .macro MXU_CHECK_BOUNDS val:req, lo_bound:req, hi_bound:req
  155.  .if (\val) < (\lo_bound) || (\val) > (\hi_bound)
  156.    .error "MXU opcode field out of range [ \lo_bound .. \hi_bound ] : \val"
  157.  .endif
  158. .endm
  159.  
  160. .macro MXU_CHECK_OFFSET val:req, byte_alignment:req, lo_bound:req, hi_bound:req
  161.  .if (\val) & (\byte_alignment - 1)
  162.    .error "MXU opcode immediate offset misaligned: \val"
  163.  .endif
  164.  .if (\val) < (\lo_bound) || (\val) > (\hi_bound)
  165.    .error "MXU opcode immediate offset out of range [ \lo_bound .. \hi_bound ] : \val"
  166.  .endif
  167. .endm
  168.  
  169. .macro MXU_CHECK_PATTERN ptn:req, lo_bound:req, hi_bound:req
  170.  .if (MXU_PTN_\ptn) < (\lo_bound) || (MXU_PTN_\ptn) > (\hi_bound)
  171.    .error "MXU opcode pattern field out of range [ ptn\lo_bound .. ptn\hi_bound ] : \ptn"
  172.  .endif
  173. .endm
  174.  
  175.  
  176. .macro d16mul      xra:req, xrb:req, xrc:req, xrd:req, optn2:req
  177.  .word 0x70000008 | (MXU_OPTN2_\optn2 << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  178. .endm
  179. .macro d16mulf     xra:req, xrb:req, xrc:req, optn2:req
  180.  .word 0x70000009 | (MXU_OPTN2_\optn2 << 22) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  181. .endm
  182. .macro d16mule     xra:req, xrb:req, xrc:req, xrd:req, optn2:req
  183.  .word 0x71000009 | (MXU_OPTN2_\optn2 << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  184. .endm
  185. .macro d16mac      xra:req, xrb:req, xrc:req, xrd:req, aptn2:req, optn2:req
  186.  .word 0x7000000a | (MXU_APTN2_\aptn2 << 24) | (MXU_OPTN2_\optn2 << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  187. .endm
  188. .macro d16macf     xra:req, xrb:req, xrc:req, xrd:req, aptn2:req, optn2:req
  189.  .word 0x7000000b | (MXU_APTN2_\aptn2 << 24) | (MXU_OPTN2_\optn2 << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  190. .endm
  191. .macro d16madl     xra:req, xrb:req, xrc:req, xrd:req, aptn2:req, optn2:req
  192.  .word 0x7000000c | (MXU_APTN2_\aptn2 << 24) | (MXU_OPTN2_\optn2 << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  193. .endm
  194. .macro s16mad      xra:req, xrb:req, xrc:req, xrd:req, aptn1:req, mptn2:req
  195.  .word 0x7000000d | (MXU_APTN1_\aptn1 << 24) | (MXU_MPTN2_\mptn2 << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  196. .endm
  197. .macro q16add      xra:req, xrb:req, xrc:req, xrd:req, aptn2:req, optn2:req
  198.  .word 0x7000000e | (MXU_APTN2_\aptn2 << 24) | (MXU_OPTN2_\optn2 << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  199. .endm
  200. .macro d16mace     xra:req, xrb:req, xrc:req, xrd:req, aptn2:req, optn2:req
  201.  .word 0x7000000f | (MXU_APTN2_\aptn2 << 24) | (MXU_OPTN2_\optn2 << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  202. .endm
  203.  
  204.  
  205. .macro q8mul       xra:req, xrb:req, xrc:req, xrd:req
  206.  .word 0x70000038 | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  207. .endm
  208. .macro q8mulsu     xra:req, xrb:req, xrc:req, xrd:req
  209.  .word 0x70800038 | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  210. .endm
  211. .macro q8mac       xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  212.  .word 0x7000003a | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  213. .endm
  214. .macro q8macsu     xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  215.  .word 0x7080003a | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  216. .endm
  217. .macro q8madl      xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  218.  .word 0x7000003c | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  219. .endm
  220.  
  221.  
  222. .macro q8movz      xra:req, xrb:req, xrc:req
  223.  .word 0x70000039 | (0 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  224. .endm
  225. .macro q8movn      xra:req, xrb:req, xrc:req
  226.  .word 0x70000039 | (1 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  227. .endm
  228. .macro d16movz     xra:req, xrb:req, xrc:req
  229.  .word 0x70000039 | (2 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  230. .endm
  231. .macro d16movn     xra:req, xrb:req, xrc:req
  232.  .word 0x70000039 | (3 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  233. .endm
  234. .macro s32movz     xra:req, xrb:req, xrc:req
  235.  .word 0x70000039 | (4 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  236. .endm
  237. .macro s32movn     xra:req, xrb:req, xrc:req
  238.  .word 0x70000039 | (5 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  239. .endm
  240.  
  241.  
  242. .macro q16scop     xra:req, xrb:req, xrc:req, xrd:req
  243.  .word 0x7000003b | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  244. .endm
  245. .macro s32sfl      xra:req, xrb:req, xrc:req, xrd:req, ptn:req
  246.  MXU_CHECK_PATTERN \ptn, 0, 3
  247.  .word 0x7000003d | (MXU_PTN_\ptn << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  248. .endm
  249. .macro q8sad       xra:req, xrb:req, xrc:req, xrd:req
  250.  .word 0x7000003e | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  251. .endm
  252.  
  253.  
  254. .macro d32add      xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  255.  .word 0x70000018 | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  256. .endm
  257. .macro d32addc     xra:req, xrb:req, xrc:req, xrd:req
  258.  .word 0x70400018 | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  259. .endm
  260. .macro d32acc      xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  261.  .word 0x70000019 | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  262. .endm
  263. .macro d32accm     xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  264.  .word 0x70400019 | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  265. .endm
  266. .macro d32asum     xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  267.  .word 0x70800019 | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  268. .endm
  269. .macro q16acc      xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  270.  .word 0x7000001b | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  271. .endm
  272. .macro q16accm     xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  273.  .word 0x7040001b | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  274. .endm
  275. .macro d16asum     xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  276.  .word 0x7080001b | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  277. .endm
  278. .macro q8adde      xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  279.  .word 0x7000001c | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  280. .endm
  281. .macro d8sum       xra:req, xrb:req, xrc:req
  282.  .word 0x7040001c | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  283. .endm
  284. .macro d8sumc      xra:req, xrb:req, xrc:req
  285.  .word 0x7080001c | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  286. .endm
  287. .macro q8acce      xra:req, xrb:req, xrc:req, xrd:req, aptn2:req
  288.  .word 0x7000001d | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  289. .endm
  290.  
  291.  
  292. .macro s32cps      xra:req, xrb:req, xrc:req
  293.  .word 0x70000007 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  294. .endm
  295. .macro d16cps      xra:req, xrb:req, xrc:req
  296.  .word 0x70080007 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  297. .endm
  298. .macro q8abd       xra:req, xrb:req, xrc:req
  299.  .word 0x70100007 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  300. .endm
  301. .macro q16sat      xra:req, xrb:req, xrc:req
  302.  .word 0x70180007 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  303. .endm
  304. .macro s32slt      xra:req, xrb:req, xrc:req
  305.  .word 0x70000006 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  306. .endm
  307. .macro d16slt      xra:req, xrb:req, xrc:req
  308.  .word 0x70040006 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  309. .endm
  310. .macro d16avg      xra:req, xrb:req, xrc:req
  311.  .word 0x70080006 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  312. .endm
  313. .macro d16avgr     xra:req, xrb:req, xrc:req
  314.  .word 0x700c0006 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  315. .endm
  316. .macro q8avg       xra:req, xrb:req, xrc:req
  317.  .word 0x70100006 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  318. .endm
  319. .macro q8avgr      xra:req, xrb:req, xrc:req
  320.  .word 0x70140006 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  321. .endm
  322. .macro q8add       xra:req, xrb:req, xrc:req, aptn2:req
  323.  .word 0x701c0006 | (MXU_APTN2_\aptn2 << 24) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  324. .endm
  325. .macro s32max      xra:req, xrb:req, xrc:req
  326.  .word 0x70000003 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  327. .endm
  328. .macro s32min      xra:req, xrb:req, xrc:req
  329.  .word 0x70040003 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  330. .endm
  331. .macro d16max      xra:req, xrb:req, xrc:req
  332.  .word 0x70080003 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  333. .endm
  334. .macro d16min      xra:req, xrb:req, xrc:req
  335.  .word 0x700c0003 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  336. .endm
  337. .macro q8max       xra:req, xrb:req, xrc:req
  338.  .word 0x70100003 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  339. .endm
  340. .macro q8min       xra:req, xrb:req, xrc:req
  341.  .word 0x70140003 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  342. .endm
  343. .macro q8slt       xra:req, xrb:req, xrc:req
  344.  .word 0x70180003 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  345. .endm
  346. .macro q8sltu      xra:req, xrb:req, xrc:req
  347.  .word 0x701c0003 | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  348. .endm
  349.  
  350.  
  351. .macro d32sll      xra:req, xrb:req, xrc:req, xrd:req, sft4:req
  352.  MXU_CHECK_BOUNDS \sft4, 0, 15
  353.  .word 0x70000030 | ((\sft4) << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  354. .endm
  355. .macro d32slr      xra:req, xrb:req, xrc:req, xrd:req, sft4:req
  356.  MXU_CHECK_BOUNDS \sft4, 0, 15
  357.  .word 0x70000031 | ((\sft4) << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  358. .endm
  359. .macro d32sarl     xra:req, xrb:req, xrc:req, sft4:req
  360.  MXU_CHECK_BOUNDS \sft4, 0, 15
  361.  .word 0x70000032 | ((\sft4) << 22) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  362. .endm
  363. .macro d32sar      xra:req, xrb:req, xrc:req, xrd:req, sft4:req
  364.  MXU_CHECK_BOUNDS \sft4, 0, 15
  365.  .word 0x70000033 | ((\sft4) << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  366. .endm
  367. .macro q16sll      xra:req, xrb:req, xrc:req, xrd:req, sft4:req
  368.  MXU_CHECK_BOUNDS \sft4, 0, 15
  369.  .word 0x70000034 | ((\sft4) << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  370. .endm
  371. .macro q16slr      xra:req, xrb:req, xrc:req, xrd:req, sft4:req
  372.  MXU_CHECK_BOUNDS \sft4, 0, 15
  373.  .word 0x70000035 | ((\sft4) << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  374. .endm
  375. .macro q16sar      xra:req, xrb:req, xrc:req, xrd:req, sft4:req
  376.  MXU_CHECK_BOUNDS \sft4, 0, 15
  377.  .word 0x70000037 | ((\sft4) << 22) | (MXU_\xrd << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  378. .endm
  379.  
  380.  
  381. .macro d32sllv     xra:req, xrd:req, rs:req
  382.  .word 0x70000036 | (GPR_\rs << 21) | (0 << 18) | (MXU_\xrd << 14) | (MXU_\xra << 10)
  383. .endm
  384. .macro d32slrv     xra:req, xrd:req, rs:req
  385.  .word 0x70000036 | (GPR_\rs << 21) | (1 << 18) | (MXU_\xrd << 14) | (MXU_\xra << 10)
  386. .endm
  387. .macro d32sarv     xra:req, xrd:req, rs:req
  388.  .word 0x70000036 | (GPR_\rs << 21) | (3 << 18) | (MXU_\xrd << 14) | (MXU_\xra << 10)
  389. .endm
  390. .macro q16sllv     xra:req, xrd:req, rs:req
  391.  .word 0x70000036 | (GPR_\rs << 21) | (4 << 18) | (MXU_\xrd << 14) | (MXU_\xra << 10)
  392. .endm
  393. .macro q16slrv     xra:req, xrd:req, rs:req
  394.  .word 0x70000036 | (GPR_\rs << 21) | (5 << 18) | (MXU_\xrd << 14) | (MXU_\xra << 10)
  395. .endm
  396. .macro q16sarv     xra:req, xrd:req, rs:req
  397.  .word 0x70000036 | (GPR_\rs << 21) | (7 << 18) | (MXU_\xrd << 14) | (MXU_\xra << 10)
  398. .endm
  399.  
  400.  
  401. .macro s32madd     xra:req, xrd:req, rs:req, rt:req
  402.  .word 0x70008000 | (GPR_\rs << 21) | (GPR_\rt << 16) | (MXU_\xrd << 10) | (MXU_\xra << 6)
  403. .endm
  404. .macro s32maddu    xra:req, xrd:req, rs:req, rt:req
  405.  .word 0x70008001 | (GPR_\rs << 21) | (GPR_\rt << 16) | (MXU_\xrd << 10) | (MXU_\xra << 6)
  406. .endm
  407. .macro s32msub     xra:req, xrd:req, rs:req, rt:req
  408.  .word 0x70008004 | (GPR_\rs << 21) | (GPR_\rt << 16) | (MXU_\xrd << 10) | (MXU_\xra << 6)
  409. .endm
  410. .macro s32msubu    xra:req, xrd:req, rs:req, rt:req
  411.  .word 0x70008005 | (GPR_\rs << 21) | (GPR_\rt << 16) | (MXU_\xrd << 10) | (MXU_\xra << 6)
  412. .endm
  413.  
  414.  
  415. .macro s32mul      xra:req, xrd:req, rs:req, rt:req
  416.  .word 0x70000026 | (GPR_\rs << 21) | (GPR_\rt << 16) | (MXU_\xrd << 10) | (MXU_\xra << 6)
  417. .endm
  418. .macro s32mulu     xra:req, xrd:req, rs:req, rt:req
  419.  .word 0x70004026 | (GPR_\rs << 21) | (GPR_\rt << 16) | (MXU_\xrd << 10) | (MXU_\xra << 6)
  420. .endm
  421. .macro s32extr     xra:req, xrd:req, rs:req, bits5:req
  422.  MXU_CHECK_BOUNDS \bits5, 1, 31
  423.  .word 0x70008026 | (GPR_\rs << 21) | ((\bits5) << 16) | (MXU_\xrd << 10) | (MXU_\xra << 6)
  424. .endm
  425. .macro s32extrv    xra:req, xrd:req, rs:req, rt:req
  426.  .word 0x7000c026 | (GPR_\rs << 21) | (GPR_\rt << 16) | (MXU_\xrd << 10) | (MXU_\xra << 6)
  427. .endm
  428.  
  429.  
  430. # XXX: The Ingenic MXU PDF dated June 2, 2017 containing MXU encodings table
  431. #  appears to list this opcode group in the wrong order with regard to the 3-bit
  432. #  minor field at bit 18. The order we use here instead matches their unofficial
  433. #  unofficial binutils patch as well as the 'mxu_as' script from CI20 MPlayer.
  434. #  'X1000_M200_XBurst_ISA_MXU_PM.pdf' is the name of the errant PDF doc.
  435. #
  436. .macro d32sarw     xra:req, xrb:req, xrc:req, rs:req
  437.  .word 0x70000027 | (GPR_\rs << 21) | (0 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  438. .endm
  439. .macro s32aln      xra:req, xrb:req, xrc:req, rs:req
  440.  .word 0x70000027 | (GPR_\rs << 21) | (1 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  441. .endm
  442. .macro s32alni     xra:req, xrb:req, xrc:req, ptn:req
  443.  MXU_CHECK_PATTERN \ptn, 0, 4
  444.  .word 0x70000027 | (MXU_PTN_\ptn << 23) | (2 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  445. .endm
  446. .macro s32lui      xra:req, imm8:req, ptn:req
  447.  MXU_CHECK_PATTERN \ptn, 0, 7
  448.  .if (\imm8) < 0
  449.    MXU_CHECK_BOUNDS \imm8, -128, 127
  450.  .else
  451.    MXU_CHECK_BOUNDS \imm8, 0, 255
  452.  .endif
  453.  .word 0x70000027 | (MXU_PTN_\ptn << 23) | (3 << 18) | (((\imm8) & 0xff) << 10) | (MXU_\xra << 6)
  454. .endm
  455. .macro s32nor      xra:req, xrb:req, xrc:req
  456.  .word 0x70000027 | (4 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  457. .endm
  458. .macro s32and      xra:req, xrb:req, xrc:req
  459.  .word 0x70000027 | (5 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  460. .endm
  461. .macro s32or       xra:req, xrb:req, xrc:req
  462.  .word 0x70000027 | (6 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  463. .endm
  464. .macro s32xor      xra:req, xrb:req, xrc:req
  465.  .word 0x70000027 | (7 << 18) | (MXU_\xrc << 14) | (MXU_\xrb << 10) | (MXU_\xra << 6)
  466. .endm
  467.  
  468.  
  469. .macro s32i2m      xra:req, rt:req
  470.  .word 0x7000002f | (GPR_\rt << 16) | (MXU_I2M_M2I_\xra << 6)
  471. .endm
  472. .macro s32m2i      xra:req, rt:req
  473.  .word 0x7000002e | (GPR_\rt << 16) | (MXU_I2M_M2I_\xra << 6)
  474. .endm
  475.  
  476.  
  477. .macro s32lddv     xra:req, rs:req, rt:req, strd2:req
  478.  MXU_CHECK_BOUNDS \strd2, 0, 2
  479.  .word 0x70000012 | (GPR_\rs << 21) | (GPR_\rt << 16) | ((\strd2) << 14) | (MXU_\xra << 6)
  480. .endm
  481. .macro s32lddvr    xra:req, rs:req, rt:req, strd2:req
  482.  MXU_CHECK_BOUNDS \strd2, 0, 2
  483.  .word 0x70000412 | (GPR_\rs << 21) | (GPR_\rt << 16) | ((\strd2) << 14) | (MXU_\xra << 6)
  484. .endm
  485. .macro s32stdv     xra:req, rs:req, rt:req, strd2:req
  486.  MXU_CHECK_BOUNDS \strd2, 0, 2
  487.  .word 0x70000013 | (GPR_\rs << 21) | (GPR_\rt << 16) | ((\strd2) << 14) | (MXU_\xra << 6)
  488. .endm
  489. .macro s32stdvr    xra:req, rs:req, rt:req, strd2:req
  490.  MXU_CHECK_BOUNDS \strd2, 0, 2
  491.  .word 0x70000413 | (GPR_\rs << 21) | (GPR_\rt << 16) | ((\strd2) << 14) | (MXU_\xra << 6)
  492. .endm
  493. .macro s32ldiv     xra:req, rs:req, rt:req, strd2:req
  494.  MXU_CHECK_BOUNDS \strd2, 0, 2
  495.  .word 0x70000016 | (GPR_\rs << 21) | (GPR_\rt << 16) | ((\strd2) << 14) | (MXU_\xra << 6)
  496. .endm
  497. .macro s32ldivr    xra:req, rs:req, rt:req, strd2:req
  498.  MXU_CHECK_BOUNDS \strd2, 0, 2
  499.  .word 0x70000416 | (GPR_\rs << 21) | (GPR_\rt << 16) | ((\strd2) << 14) | (MXU_\xra << 6)
  500. .endm
  501. .macro s32sdiv     xra:req, rs:req, rt:req, strd2:req
  502.  MXU_CHECK_BOUNDS \strd2, 0, 2
  503.  .word 0x70000017 | (GPR_\rs << 21) | (GPR_\rt << 16) | ((\strd2) << 14) | (MXU_\xra << 6)
  504. .endm
  505. .macro s32sdivr    xra:req, rs:req, rt:req, strd2:req
  506.  MXU_CHECK_BOUNDS \strd2, 0, 2
  507.  .word 0x70000417 | (GPR_\rs << 21) | (GPR_\rt << 16) | ((\strd2) << 14) | (MXU_\xra << 6)
  508. .endm
  509.  
  510.  
  511. .macro s32ldd      xra:req, rs:req, imm12:req
  512.  MXU_CHECK_OFFSET \imm12, 4, -2048, 2047
  513.  .word 0x70000010 | (GPR_\rs << 21) | (((\imm12) & 0xffc) << 8) | (MXU_\xra << 6)
  514. .endm
  515. .macro s32lddr     xra:req, rs:req, imm12:req
  516.  MXU_CHECK_OFFSET \imm12, 4, -2048, 2047
  517.  .word 0x70100010 | (GPR_\rs << 21) | (((\imm12) & 0xffc) << 8) | (MXU_\xra << 6)
  518. .endm
  519. .macro s32std      xra:req, rs:req, imm12:req
  520.  MXU_CHECK_OFFSET \imm12, 4, -2048, 2047
  521.  .word 0x70000011 | (GPR_\rs << 21) | (((\imm12) & 0xffc) << 8) | (MXU_\xra << 6)
  522. .endm
  523. .macro s32stdr     xra:req, rs:req, imm12:req
  524.  MXU_CHECK_OFFSET \imm12, 4, -2048, 2047
  525.  .word 0x70100011 | (GPR_\rs << 21) | (((\imm12) & 0xffc) << 8) | (MXU_\xra << 6)
  526. .endm
  527. .macro s32ldi      xra:req, rs:req, imm12:req
  528.  MXU_CHECK_OFFSET \imm12, 4, -2048, 2047
  529.  .word 0x70000014 | (GPR_\rs << 21) | (((\imm12) & 0xffc) << 8) | (MXU_\xra << 6)
  530. .endm
  531. .macro s32ldir     xra:req, rs:req, imm12:req
  532.  MXU_CHECK_OFFSET \imm12, 4, -2048, 2047
  533.  .word 0x70100014 | (GPR_\rs << 21) | (((\imm12) & 0xffc) << 8) | (MXU_\xra << 6)
  534. .endm
  535. .macro s32sdi      xra:req, rs:req, imm12:req
  536.  MXU_CHECK_OFFSET \imm12, 4, -2048, 2047
  537.  .word 0x70000015 | (GPR_\rs << 21) | (((\imm12) & 0xffc) << 8) | (MXU_\xra << 6)
  538. .endm
  539. .macro s32sdir     xra:req, rs:req, imm12:req
  540.  MXU_CHECK_OFFSET \imm12, 4, -2048, 2047
  541.  .word 0x70100015 | (GPR_\rs << 21) | (((\imm12) & 0xffc) << 8) | (MXU_\xra << 6)
  542. .endm
  543.  
  544.  
  545. .macro s8ldd       xra:req, rs:req, imm8:req, ptn:req
  546.  MXU_CHECK_OFFSET  \imm8, 1, -128, 127
  547.  MXU_CHECK_PATTERN \ptn, 0, 7
  548.  .word 0x70000022 | (GPR_\rs << 21) | (MXU_PTN_\ptn << 18) | (((\imm8) & 0xff) << 10) | (MXU_\xra << 6)
  549. .endm
  550. .macro s8std       xra:req, rs:req, imm8:req, ptn:req
  551.  MXU_CHECK_OFFSET  \imm8, 1, -128, 127
  552.  MXU_CHECK_PATTERN \ptn, 0, 3
  553.  .word 0x70000023 | (GPR_\rs << 21) | (MXU_PTN_\ptn << 18) | (((\imm8) & 0xff) << 10) | (MXU_\xra << 6)
  554. .endm
  555. .macro s8ldi       xra:req, rs:req, imm8:req, ptn:req
  556.  MXU_CHECK_OFFSET  \imm8, 1, -128, 127
  557.  MXU_CHECK_PATTERN \ptn, 0, 7
  558.  .word 0x70000024 | (GPR_\rs << 21) | (MXU_PTN_\ptn << 18) | (((\imm8) & 0xff) << 10) | (MXU_\xra << 6)
  559. .endm
  560. .macro s8sdi       xra:req, rs:req, imm8:req, ptn:req
  561.  MXU_CHECK_OFFSET  \imm8, 1, -128, 127
  562.  MXU_CHECK_PATTERN \ptn, 0, 3
  563.  .word 0x70000025 | (GPR_\rs << 21) | (MXU_PTN_\ptn << 18) | (((\imm8) & 0xff) << 10) | (MXU_\xra << 6)
  564. .endm
  565. .macro s16ldd      xra:req, rs:req, imm10:req, ptn:req
  566.  MXU_CHECK_OFFSET  \imm10, 2, -512, 511
  567.  MXU_CHECK_PATTERN \ptn, 0, 3
  568.  .word 0x7000002a | (GPR_\rs << 21) | (MXU_PTN_\ptn << 19) | (((\imm10) & 0x3fe) << 9) | (MXU_\xra << 6)
  569. .endm
  570. .macro s16std      xra:req, rs:req, imm10:req, ptn:req
  571.  MXU_CHECK_OFFSET  \imm10, 2, -512, 511
  572.  MXU_CHECK_PATTERN \ptn, 0, 1
  573.  .word 0x7000002b | (GPR_\rs << 21) | (MXU_PTN_\ptn << 19) | (((\imm10) & 0x3fe) << 9) | (MXU_\xra << 6)
  574. .endm
  575. .macro s16ldi      xra:req, rs:req, imm10:req, ptn:req
  576.  MXU_CHECK_OFFSET  \imm10, 2, -512, 511
  577.  MXU_CHECK_PATTERN \ptn, 0, 3
  578.  .word 0x7000002c | (GPR_\rs << 21) | (MXU_PTN_\ptn << 19) | (((\imm10) & 0x3fe) << 9) | (MXU_\xra << 6)
  579. .endm
  580. .macro s16sdi      xra:req, rs:req, imm10:req, ptn:req
  581.  MXU_CHECK_OFFSET \imm10, 2, -512, 511
  582.  MXU_CHECK_PATTERN \ptn, 0, 1
  583.  .word 0x7000002d | (GPR_\rs << 21) | (MXU_PTN_\ptn << 19) | (((\imm10) & 0x3fe) << 9) | (MXU_\xra << 6)
  584. .endm
  585.  
  586.  
  587. .macro lxw         rd:req, rs:req, rt:req, strd2:req
  588.  MXU_CHECK_BOUNDS \strd2, 0, 2
  589.  .word 0x70000028 | (GPR_\rs << 21) | (GPR_\rt << 16) | (GPR_\rd << 11) | ((\strd2) << 9) | (3 << 6)
  590. .endm
  591. .macro lxh         rd:req, rs:req, rt:req, strd2:req
  592.  MXU_CHECK_BOUNDS \strd2, 0, 2
  593.  .word 0x70000028 | (GPR_\rs << 21) | (GPR_\rt << 16) | (GPR_\rd << 11) | ((\strd2) << 9) | (1 << 6)
  594. .endm
  595. .macro lxhu        rd:req, rs:req, rt:req, strd2:req
  596.  MXU_CHECK_BOUNDS \strd2, 0, 2
  597.  .word 0x70000028 | (GPR_\rs << 21) | (GPR_\rt << 16) | (GPR_\rd << 11) | ((\strd2) << 9) | (5 << 6)
  598. .endm
  599. .macro lxb         rd:req, rs:req, rt:req, strd2:req
  600.  MXU_CHECK_BOUNDS \strd2, 0, 2
  601.  .word 0x70000028 | (GPR_\rs << 21) | (GPR_\rt << 16) | (GPR_\rd << 11) | ((\strd2) << 9) | (0 << 6)
  602. .endm
  603. .macro lxbu        rd:req, rs:req, rt:req, strd2:req
  604.  MXU_CHECK_BOUNDS \strd2, 0, 2
  605.  .word 0x70000028 | (GPR_\rs << 21) | (GPR_\rt << 16) | (GPR_\rd << 11) | ((\strd2) << 9) | (4 << 6)
  606. .endm
  607.  
  608.  
  609. .endif # MXU1_AS_MACROS_S_H
  610.  
  611. # vim:shiftwidth=2:expandtab:syntax=asm
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