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Release 14.4 - xst P.49d (lin64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 4.00 secs Total CPU time to Xst completion: 0.09 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 4.00 secs Total CPU time to Xst completion: 0.09 secs --> Reading design: vedic_div32.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "vedic_div32.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "vedic_div32" Output Format : NGC Target Device : xc5vlx50t-1-ff1136 ---- Source Options Top Module Name : vedic_div32 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : Yes Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : Yes Resource Sharing : NO Asynchronous To Synchronous : NO Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 32 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 2 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" in Library work. Entity <vedic_div32> compiled. Entity <vedic_div32> (Architecture <rtl>) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>). WARNING:Xst:2096 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 84: Use of null array slice on signal <d_init_re_reg> is not supported. WARNING:Xst:2096 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 85: Use of null array slice on signal <init_reg.re_reg> is not supported. INFO:Xst:2679 - Register <d_init_quo_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register <init_reg.re_reg<35>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register <init_reg.re_reg<34>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register <init_reg.re_reg<33>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register <init_reg.re_reg<32>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register <init_reg.re_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit <vedic_div32>. Related source file is "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd". WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000. WARNING:Xst:646 - Signal <d_state> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <d_re_tmp> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <d_re> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <d_main_re_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal <d_init_re_reg<31>> is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <d_init_re_reg<30:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <d_init_quo_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 9 | | Inputs | 3 | | Outputs | 4 | | Clock | mclk1 (rising_edge) | | Reset | state$and0000 (positive) | | Reset type | synchronous | | Reset State | fin_state | | Power Up State | init_state | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 123: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 122: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. Found 34x4-bit multiplier for signal <$mult0000> created at line 207. Found 34x5-bit multiplier for signal <$mult0001> created at line 207. Found 34x4-bit multiplier for signal <$mult0002> created at line 207. Found 34x5-bit multiplier for signal <$mult0003> created at line 207. Found 31-bit register for signal <b_n>. Found 5-bit register for signal <i>. Found 5-bit subtractor for signal <i$addsub0000> created at line 155. Found 32-bit register for signal <i_quo>. Found 32-bit register for signal <i_re>. Found 32-bit register for signal <init_reg.quo_reg>. Found 31-bit register for signal <init_reg.re_reg<30:0>>. Found 32-bit register for signal <k_reg.quo>. Found 36-bit register for signal <k_reg.re_reg>. Found 1-bit register for signal <k_reg.re_sign>. Found 32-bit register for signal <main_reg.quo>. Found 32-bit adder for signal <main_reg.quo$addsub0000> created at line 115. Found 32-bit subtractor for signal <main_reg.quo$addsub0001> created at line 117. Found 32-bit register for signal <main_reg.quo_reg>. Found 32-bit adder for signal <main_reg.quo_reg$addsub0000> created at line 134. Found 1-bit register for signal <main_reg.quo_sign>. Found 36-bit register for signal <main_reg.re_reg>. Found 36-bit adder for signal <main_reg.re_reg$addsub0000> created at line 139. Found 36-bit adder for signal <main_reg.re_reg$addsub0001> created at line 144. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 138. Found 1-bit register for signal <main_reg.re_sign>. Found 32-bit adder for signal <quo$addsub0000> created at line 241. Found 32-bit adder for signal <quo$addsub0001> created at line 241. Found 32-bit adder for signal <quo$addsub0002> created at line 241. Found 32-bit adder for signal <quo$addsub0003> created at line 241. Found 32-bit adder for signal <quo$addsub0004> created at line 241. Found 32-bit adder for signal <quo$addsub0005> created at line 241. Found 32-bit adder for signal <quo$addsub0006> created at line 241. Found 32-bit adder for signal <quo$addsub0007> created at line 241. Found 32-bit subtractor for signal <quo$addsub0008> created at line 241. Found 32-bit subtractor for signal <quo$addsub0009> created at line 241. Found 32-bit subtractor for signal <quo$addsub0010> created at line 241. Found 32-bit subtractor for signal <quo$addsub0011> created at line 241. Found 32-bit subtractor for signal <quo$addsub0012> created at line 241. Found 32-bit subtractor for signal <quo$addsub0013> created at line 241. Found 32-bit subtractor for signal <quo$addsub0014> created at line 241. Found 32-bit subtractor for signal <quo$addsub0015> created at line 241. Found 33-bit subtractor for signal <quo_reg_sub$sub0000> created at line 124. Found 33x32-bit multiplier for signal <quo_tmp$mult0001> created at line 122. Found 32-bit subtractor for signal <re$addsub0000> created at line 207. Found 32-bit subtractor for signal <re$addsub0001> created at line 207. Found 32-bit subtractor for signal <re$addsub0002> created at line 207. Found 32-bit subtractor for signal <re$addsub0003> created at line 207. Found 32-bit subtractor for signal <re$addsub0004> created at line 207. Found 32-bit subtractor for signal <re$addsub0005> created at line 207. Found 32-bit subtractor for signal <re$addsub0006> created at line 207. Found 32-bit subtractor for signal <re$addsub0007> created at line 207. Found 32-bit adder for signal <re$addsub0008> created at line 207. Found 32-bit adder for signal <re$addsub0009> created at line 207. Found 32-bit adder for signal <re$addsub0010> created at line 207. Found 32-bit adder for signal <re$addsub0011> created at line 207. Found 32-bit adder for signal <re$addsub0012> created at line 207. Found 32-bit adder for signal <re$addsub0013> created at line 207. Found 32-bit adder for signal <re$addsub0014> created at line 207. Found 32-bit adder for signal <re$addsub0015> created at line 207. Found 29-bit comparator greatequal for signal <re$cmp_ge0000> created at line 207. Found 32-bit comparator greatequal for signal <re$cmp_ge0001> created at line 207. Found 31-bit comparator greatequal for signal <re$cmp_ge0002> created at line 207. Found 32-bit comparator greatequal for signal <re$cmp_ge0003> created at line 207. Found 30-bit comparator greatequal for signal <re$cmp_ge0004> created at line 207. Found 32-bit comparator greatequal for signal <re$cmp_ge0005> created at line 207. Found 31-bit comparator greatequal for signal <re$cmp_ge0006> created at line 207. Found 32-bit comparator greatequal for signal <re$cmp_ge0007> created at line 207. Found 32-bit comparator greatequal for signal <re$cmp_ge0008> created at line 207. Found 32-bit comparator greatequal for signal <re$cmp_ge0009> created at line 207. Found 31-bit comparator greatequal for signal <re$cmp_ge0010> created at line 207. Found 32-bit comparator greatequal for signal <re$cmp_ge0011> created at line 207. Found 30-bit comparator greatequal for signal <re$cmp_ge0012> created at line 207. Found 32-bit comparator greatequal for signal <re$cmp_ge0013> created at line 207. Found 31-bit comparator greatequal for signal <re$cmp_ge0014> created at line 207. Found 32-bit comparator greatequal for signal <re$cmp_ge0015> created at line 207. Found 33x4-bit multiplier for signal <re$mult0005> created at line 207. Found 33x3-bit multiplier for signal <re$mult0006> created at line 207. Found 33x4-bit multiplier for signal <re$mult0007> created at line 207. Found 33x3-bit multiplier for signal <re$mult0008> created at line 207. Found 33x3-bit multiplier for signal <re$mult0010> created at line 207. Found 33x4-bit multiplier for signal <re$mult0011> created at line 207. Found 33x4-bit multiplier for signal <re$mult0012> created at line 207. Found 32-bit adder for signal <re$sub0000> created at line 207. Found 31-bit adder for signal <re$sub0001> created at line 207. Found 32-bit adder for signal <re$sub0002> created at line 207. Found 30-bit adder for signal <re$sub0003> created at line 207. Found 32-bit adder for signal <re$sub0004> created at line 207. Found 31-bit adder for signal <re$sub0005> created at line 207. Found 32-bit adder for signal <re$sub0006> created at line 207. Found 37-bit subtractor for signal <re_reg_sub$sub0000> created at line 125. Found 33x32-bit multiplier for signal <re_tmp$mult0001> created at line 123. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 123. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 123. Found 5-bit register for signal <shift_val>. Found 32-bit register for signal <tmp_quo_reg>. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_0$mux0000> created at line 110. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_1$mux0000> created at line 110. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_2$mux0000> created at line 110. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_3$mux0000> created at line 110. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_4$mux0000> created at line 110. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_5$mux0000> created at line 110. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_6$mux0000> created at line 110. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_7$mux0000> created at line 110. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_8$mux0000> created at line 110. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_shifted_0$mux0000> created at line 112. Found 36-bit adder for signal <v_re$addsub0000> created at line 196. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 200. Found 1-bit 32-to-1 multiplexer for signal <v_reg.quo_reg_30$mux0000> created at line 120. Summary: inferred 1 Finite State Machine(s). inferred 371 D-type flip-flop(s). inferred 48 Adder/Subtractor(s). inferred 13 Multiplier(s). inferred 16 Comparator(s). inferred 42 Multiplexer(s). inferred 1 Combinational logic shifter(s). Unit <vedic_div32> synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Multipliers : 13 33x3-bit multiplier : 3 33x32-bit multiplier : 2 33x4-bit multiplier : 4 34x4-bit multiplier : 2 34x5-bit multiplier : 2 # Adders/Subtractors : 48 30-bit adder : 1 31-bit adder : 2 32-bit adder : 22 32-bit subtractor : 17 33-bit subtractor : 1 36-bit adder : 3 37-bit subtractor : 1 5-bit subtractor : 1 # Registers : 108 1-bit register : 98 31-bit register : 1 32-bit register : 5 36-bit register : 2 5-bit register : 2 # Comparators : 16 29-bit comparator greatequal : 1 30-bit comparator greatequal : 2 31-bit comparator greatequal : 4 32-bit comparator greatequal : 9 # Multiplexers : 42 1-bit 31-to-1 multiplexer : 1 1-bit 32-to-1 multiplexer : 41 # Logic shifters : 1 36-bit shifter arithmetic right : 1 # Xors : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM <FSM_0> for best encoding. Optimizing FSM <state/FSM> on signal <state[1:4]> with one-hot encoding. ------------------------ State | Encoding ------------------------ init_state | 0001 main_state | 0100 wait_state | 1000 fin_state | 0010 ------------------------ ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 # Multipliers : 13 33x3-bit multiplier : 3 33x32-bit multiplier : 2 33x4-bit multiplier : 4 34x4-bit multiplier : 2 34x5-bit multiplier : 2 # Adders/Subtractors : 48 30-bit adder : 1 31-bit adder : 2 32-bit adder : 22 32-bit subtractor : 17 33-bit subtractor : 1 36-bit adder : 3 37-bit subtractor : 1 5-bit subtractor : 1 # Registers : 370 Flip-Flops : 370 # Comparators : 16 29-bit comparator greatequal : 1 30-bit comparator greatequal : 2 31-bit comparator greatequal : 4 32-bit comparator greatequal : 9 # Multiplexers : 42 1-bit 31-to-1 multiplexer : 1 1-bit 32-to-1 multiplexer : 41 # Logic shifters : 1 36-bit shifter arithmetic right : 1 # Xors : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2677 - Node <Mmult_re_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>. WARNING:Xst:2677 - Node <Mmult_quo_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>. Optimizing unit <vedic_div32> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 23. FlipFlop i_1 has been replicated 1 time(s) Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 374 Flip-Flops : 374 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : vedic_div32.ngr Top Level Output File Name : vedic_div32 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : No Design Statistics # IOs : 130 Cell Usage : # BELS : 8946 # GND : 1 # INV : 530 # LUT1 : 258 # LUT2 : 1083 # LUT3 : 312 # LUT4 : 717 # LUT5 : 396 # LUT6 : 1516 # MUXCY : 2092 # MUXF7 : 124 # VCC : 1 # XORCY : 1916 # FlipFlops/Latches : 374 # FD : 184 # FDE : 136 # FDR : 2 # FDRE : 35 # FDRSE : 1 # FDS : 16 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 129 # IBUF : 65 # OBUF : 64 # DSPs : 6 # DSP48E : 6 ========================================================================= Device utilization summary: --------------------------- Selected Device : 5vlx50tff1136-1 Slice Logic Utilization: Number of Slice Registers: 374 out of 28800 1% Number of Slice LUTs: 4812 out of 28800 16% Number used as Logic: 4812 out of 28800 16% Slice Logic Distribution: Number of LUT Flip Flop pairs used: 4889 Number with an unused Flip Flop: 4515 out of 4889 92% Number with an unused LUT: 77 out of 4889 1% Number of fully used LUT-FF pairs: 297 out of 4889 6% Number of unique control sets: 42 IO Utilization: Number of IOs: 130 Number of bonded IOBs: 130 out of 480 27% Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 1 out of 32 3% Number of DSP48Es: 6 out of 48 12% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ mclk1 | BUFGP | 374 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -1 Minimum period: 15.216ns (Maximum Frequency: 65.720MHz) Minimum input arrival time before clock: 10.356ns Maximum output required time after clock: 11.207ns Maximum combinational path delay: 15.455ns Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'mclk1' Clock period: 15.216ns (frequency: 65.720MHz) Total number of paths / destination ports: 9231017668 / 366 ------------------------------------------------------------------------- Delay: 15.216ns (Levels of Logic = 27) Source: b_n_14 (FF) Destination: main_reg.quo_reg_31 (FF) Source Clock: mclk1 rising Destination Clock: mclk1 rising Data Path: b_n_14 to main_reg.quo_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDE:C->Q 8 0.471 1.011 b_n_14 (b_n_14) LUT5:I0->O 1 0.094 0.973 quo_tmp_mux0000<13>77 (quo_tmp_mux0000<13>77) LUT5:I0->O 1 0.094 0.000 quo_tmp_mux0000<13>151_F (N580) MUXF7:I0->O 1 0.251 0.480 quo_tmp_mux0000<13>151 (quo_tmp_mux0000<13>151) LUT6:I5->O 1 0.094 0.000 quo_tmp_mux0000<13>179_G (N599) MUXF7:I1->O 1 0.254 0.336 quo_tmp_mux0000<13>179 (quo_tmp_mux0000<13>) DSP48E:A13->PCOUT20 1 3.832 0.000 Mmult_quo_tmp_mult0001 (Mmult_quo_tmp_mult0001_PCOUT_to_Mmult_quo_tmp_mult00011_PCIN_20) DSP48E:PCIN20->PCOUT12 1 2.013 0.000 Mmult_quo_tmp_mult00011 (Mmult_quo_tmp_mult00011_PCOUT_to_Mmult_quo_tmp_mult00012_PCIN_12) DSP48E:PCIN12->P0 1 1.816 0.480 Mmult_quo_tmp_mult00012 (quo_tmp_mult0001<17>) LUT6:I5->O 1 0.094 0.000 Msub_quo_reg_sub_sub0000_lut<17> (Msub_quo_reg_sub_sub0000_lut<17>) MUXCY:S->O 1 0.372 0.000 Msub_quo_reg_sub_sub0000_cy<17> (Msub_quo_reg_sub_sub0000_cy<17>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<18> (Msub_quo_reg_sub_sub0000_cy<18>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<19> (Msub_quo_reg_sub_sub0000_cy<19>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<20> (Msub_quo_reg_sub_sub0000_cy<20>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<21> (Msub_quo_reg_sub_sub0000_cy<21>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<22> (Msub_quo_reg_sub_sub0000_cy<22>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<23> (Msub_quo_reg_sub_sub0000_cy<23>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<24> (Msub_quo_reg_sub_sub0000_cy<24>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<25> (Msub_quo_reg_sub_sub0000_cy<25>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<26> (Msub_quo_reg_sub_sub0000_cy<26>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<27> (Msub_quo_reg_sub_sub0000_cy<27>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<28> (Msub_quo_reg_sub_sub0000_cy<28>) MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<29> (Msub_quo_reg_sub_sub0000_cy<29>) XORCY:CI->O 2 0.357 0.341 Msub_quo_reg_sub_sub0000_xor<30> (quo_reg_sub_sub0000<30>) INV:I->O 1 0.238 0.000 Madd_main_reg_quo_reg_not0000<30>1_INV_0 (Madd_main_reg_quo_reg_not0000<30>) MUXCY:S->O 0 0.372 0.000 Madd_main_reg.quo_reg_addsub0000_cy<30> (Madd_main_reg.quo_reg_addsub0000_cy<30>) XORCY:CI->O 1 0.357 0.480 Madd_main_reg.quo_reg_addsub0000_xor<31> (main_reg_quo_reg_addsub0000<31>) LUT3:I2->O 1 0.094 0.000 main_reg_quo_reg_mux0000<31>1 (main_reg_quo_reg_mux0000<31>) FD:D -0.018 main_reg.quo_reg_31 ---------------------------------------- Total 15.216ns (11.115ns logic, 4.101ns route) (73.0% logic, 27.0% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1' Total number of paths / destination ports: 8558 / 243 ------------------------------------------------------------------------- Offset: 10.356ns (Levels of Logic = 15) Source: divisor<2> (PAD) Destination: b_n_29 (FF) Destination Clock: mclk1 rising Data Path: divisor<2> to b_n_29 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 127 0.818 0.721 divisor_2_IBUF (divisor_2_IBUF) LUT2:I0->O 4 0.094 0.726 b_n_mux0000<1>11111 (N806) LUT6:I3->O 2 0.094 0.794 b_n_mux0000<1>182 (b_n_mux0000<1>182) LUT6:I2->O 1 0.094 0.000 b_n_mux0000<1>245_F (N632) MUXF7:I0->O 1 0.251 0.789 b_n_mux0000<1>245 (b_n_mux0000<1>245) LUT6:I2->O 1 0.094 0.480 b_n_mux0000<1>307 (b_n_mux0000<1>307) LUT6:I5->O 1 0.094 0.000 b_n_mux0000<1>461_SW01 (b_n_mux0000<1>461_SW0) MUXF7:I1->O 1 0.254 0.576 b_n_mux0000<1>461_SW0_f7 (N260) LUT6:I4->O 1 0.094 0.789 b_n_mux0000<1>461 (b_n_mux0000<1>461) LUT6:I2->O 1 0.094 0.710 b_n_mux0000<1>508 (b_n_mux0000<1>508) LUT5:I2->O 1 0.094 0.973 b_n_mux0000<1>587_SW1 (N518) LUT6:I1->O 1 0.094 0.480 b_n_mux0000<1>587 (b_n_mux0000<1>587) LUT6:I5->O 1 0.094 0.000 b_n_mux0000<1>692_SW02 (b_n_mux0000<1>692_SW01) MUXF7:I0->O 1 0.251 0.710 b_n_mux0000<1>692_SW0_f7 (N266) LUT6:I3->O 1 0.094 0.000 b_n_mux0000<1>692 (b_n_mux0000<1>) FDE:D -0.018 b_n_29 ---------------------------------------- Total 10.356ns (2.608ns logic, 7.748ns route) (25.2% logic, 74.8% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1' Total number of paths / destination ports: 154585 / 64 ------------------------------------------------------------------------- Offset: 11.207ns (Levels of Logic = 38) Source: i_re_1 (FF) Destination: re<30> (PAD) Source Clock: mclk1 rising Data Path: i_re_1 to re<30> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 39 0.471 0.705 i_re_1 (i_re_1) LUT2:I0->O 1 0.094 0.000 Madd_re_addsub0013_lut<1> (Madd_re_addsub0013_lut<1>) MUXCY:S->O 1 0.372 0.000 Madd_re_addsub0013_cy<1> (Madd_re_addsub0013_cy<1>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<2> (Madd_re_addsub0013_cy<2>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<3> (Madd_re_addsub0013_cy<3>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<4> (Madd_re_addsub0013_cy<4>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<5> (Madd_re_addsub0013_cy<5>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<6> (Madd_re_addsub0013_cy<6>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<7> (Madd_re_addsub0013_cy<7>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<8> (Madd_re_addsub0013_cy<8>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<9> (Madd_re_addsub0013_cy<9>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<10> (Madd_re_addsub0013_cy<10>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<11> (Madd_re_addsub0013_cy<11>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<12> (Madd_re_addsub0013_cy<12>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<13> (Madd_re_addsub0013_cy<13>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<14> (Madd_re_addsub0013_cy<14>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<15> (Madd_re_addsub0013_cy<15>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<16> (Madd_re_addsub0013_cy<16>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<17> (Madd_re_addsub0013_cy<17>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<18> (Madd_re_addsub0013_cy<18>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<19> (Madd_re_addsub0013_cy<19>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<20> (Madd_re_addsub0013_cy<20>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<21> (Madd_re_addsub0013_cy<21>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<22> (Madd_re_addsub0013_cy<22>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<23> (Madd_re_addsub0013_cy<23>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<24> (Madd_re_addsub0013_cy<24>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<25> (Madd_re_addsub0013_cy<25>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<26> (Madd_re_addsub0013_cy<26>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<27> (Madd_re_addsub0013_cy<27>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<28> (Madd_re_addsub0013_cy<28>) MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<29> (Madd_re_addsub0013_cy<29>) XORCY:CI->O 1 0.357 0.973 Madd_re_addsub0013_xor<30> (re_addsub0013<30>) LUT6:I1->O 1 0.094 0.710 re<30>66 (re<30>66) LUT6:I3->O 1 0.094 0.973 re<30>93 (re<30>93) LUT5:I0->O 1 0.094 0.789 re<30>125 (re<30>125) LUT6:I2->O 1 0.094 0.710 re<30>194_SW0 (N292) LUT6:I3->O 1 0.094 0.973 re<30>194 (re<30>194) LUT5:I0->O 1 0.094 0.336 re<30>233 (re_30_OBUF) OBUF:I->O 2.452 re_30_OBUF (re<30>) ---------------------------------------- Total 11.207ns (5.038ns logic, 6.169ns route) (45.0% logic, 55.0% route) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 82339987 / 64 ------------------------------------------------------------------------- Delay: 15.455ns (Levels of Logic = 45) Source: divisor<2> (PAD) Destination: quo<31> (PAD) Data Path: divisor<2> to quo<31> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 127 0.818 0.721 divisor_2_IBUF (divisor_2_IBUF) LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0012_Madd_lut<2> (Mmult_re_mult0012_Madd_lut<2>) MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0012_Madd_cy<2> (Mmult_re_mult0012_Madd_cy<2>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<3> (Mmult_re_mult0012_Madd_cy<3>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<4> (Mmult_re_mult0012_Madd_cy<4>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<5> (Mmult_re_mult0012_Madd_cy<5>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<6> (Mmult_re_mult0012_Madd_cy<6>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<7> (Mmult_re_mult0012_Madd_cy<7>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<8> (Mmult_re_mult0012_Madd_cy<8>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<9> (Mmult_re_mult0012_Madd_cy<9>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<10> (Mmult_re_mult0012_Madd_cy<10>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<11> (Mmult_re_mult0012_Madd_cy<11>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<12> (Mmult_re_mult0012_Madd_cy<12>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<13> (Mmult_re_mult0012_Madd_cy<13>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<14> (Mmult_re_mult0012_Madd_cy<14>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<15> (Mmult_re_mult0012_Madd_cy<15>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<16> (Mmult_re_mult0012_Madd_cy<16>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<17> (Mmult_re_mult0012_Madd_cy<17>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<18> (Mmult_re_mult0012_Madd_cy<18>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<19> (Mmult_re_mult0012_Madd_cy<19>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<20> (Mmult_re_mult0012_Madd_cy<20>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<21> (Mmult_re_mult0012_Madd_cy<21>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<22> (Mmult_re_mult0012_Madd_cy<22>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<23> (Mmult_re_mult0012_Madd_cy<23>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<24> (Mmult_re_mult0012_Madd_cy<24>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<25> (Mmult_re_mult0012_Madd_cy<25>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<26> (Mmult_re_mult0012_Madd_cy<26>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<27> (Mmult_re_mult0012_Madd_cy<27>) MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<28> (Mmult_re_mult0012_Madd_cy<28>) XORCY:CI->O 1 0.357 0.576 Mmult_re_mult0012_Madd_xor<29> (Mmult_re_mult0012_Madd_29) LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0012_Madd1_lut<29> (Mmult_re_mult0012_Madd1_lut<29>) MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0012_Madd1_cy<29> (Mmult_re_mult0012_Madd1_cy<29>) XORCY:CI->O 1 0.357 0.336 Mmult_re_mult0012_Madd1_xor<30> (re_mult0012<30>) INV:I->O 1 0.238 0.000 Madd_re_not0006<30>1_INV_0 (Madd_re_not0006<30>) MUXCY:S->O 0 0.372 0.000 Madd_re_sub0006_cy<30> (Madd_re_sub0006_cy<30>) XORCY:CI->O 2 0.357 0.794 Madd_re_sub0006_xor<31> (re_sub0006<31>) LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0015_lutdi15 (Mcompar_re_cmp_ge0015_lutdi15) MUXCY:DI->O 8 0.590 0.518 Mcompar_re_cmp_ge0015_cy<15> (re_cmp_ge0015) LUT4:I3->O 61 0.094 0.922 quo<2>1111 (N656) LUT6:I2->O 1 0.094 0.973 re<9>93 (re<9>93) LUT5:I0->O 1 0.094 0.789 re<9>125 (re<9>125) LUT6:I2->O 1 0.094 0.710 re<9>194_SW0 (N278) LUT6:I3->O 1 0.094 0.973 re<9>194 (re<9>194) LUT5:I0->O 1 0.094 0.336 re<9>233 (re_9_OBUF) OBUF:I->O 2.452 re_9_OBUF (re<9>) ---------------------------------------- Total 15.455ns (7.807ns logic, 7.648ns route) (50.5% logic, 49.5% route) ========================================================================= Total REAL time to Xst completion: 2155.00 secs Total CPU time to Xst completion: 2136.24 secs --> Total memory usage is 910484 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 25 ( 0 filtered) Number of infos : 6 ( 0 filtered)
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