module proj1_test();
  wire clk, reset; //clock and reset
  reg [7:0] in;
  wire [7:0] out; //input and output
  reg eof;

  integer data_file;
  initial
    data_file=$fopen("proj1.dat", "rb");


  always@(posedge clk)
  begin
    eof=$feof(data_file);
    if(eof==0)
      $fscanf(data_file, "%d", in);
  end



  init #(4) my_init(reset, clk);

  project1 proj1(clk, reset, in, out);

endmodule