ffjk

-- Descrição do flip-flop JK
library ieee;
use ieee.std_logic_1164.all;

entity ffjk is
    port(
        j: in std_logic;
        k: in std_logic;
        clk: in std_logic;
        clr: in std_logic;
        q: out std_logic
        );
end ffjk;

architecture funcional of ffjk is
signal qaux: std_logic := '0';
begin
    process(clk,clr)
    begin
        if clr = '0' then
            qaux <= '0';
        elsif falling_edge(clk) then
            if j = '0' and k = '1' then
                qaux <= '0';
            elsif j = '1' and k = '0' then
                qaux <= '1';
            elsif j = '1' and k = '1' then
                qaux <= not qaux;
            end if;
        end if;
    end process;
    q <= qaux;
end funcional;