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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity pulse is
  6. generic(N: integer range 0 to 32 := 8);
  7. port (
  8. clk    : in std_logic; 
  9. reset  : in std_logic;                          
  10. trig   : in std_logic;                           
  11. pulse_len  : in UNSIGNED(N-1 downto 0);  
  12. wave   : out std_logic);
  13. end pulse;
  14.  
  15.  
  16. architecture rtl of pulse is
  17.  
  18. type FSM is (CZUWAJ, GENERUJ);
  19.  
  20. signal stan, stan_nast: FSM;
  21. signal stoper, zapisane_pl: UNSIGNED(N-1 downto 0);
  22. signal zeruj: std_logic;
  23.  
  24. begin
  25.  
  26. STATE_REG_PROC:
  27. process (clk,reset)
  28. begin
  29. if (reset = '0') then
  30.   stan <= CZUWAJ;
  31. elsif (rising_edge(clk)) then
  32.   stan <= stan_nast;
  33. end if;
  34. end process;
  35.  
  36.  
  37. NEXT_STATE_PROC:
  38. process (stan,trig,clk)
  39. begin
  40.     case stan is
  41.     when GENERUJ =>
  42.       if ((stoper >= zapisane_pl-1) or (trig = '1')) then
  43.         stan_nast <= CZUWAJ;
  44.         zeruj <= '1';
  45.       else
  46.         stan_nast <= GENERUJ;
  47.         zeruj <= '0';
  48.       end if;
  49.     when CZUWAJ =>
  50.       if(trig='1' and not (zapisane_pl = 0)) then
  51.         stan_nast <= GENERUJ;
  52.         zeruj <= '1';
  53.       else
  54.         stan_nast <= CZUWAJ;
  55.         zeruj <= '0';
  56.       end if;
  57.     end case;
  58. end process;
  59.  
  60.  
  61. WAVE_PROC:
  62. process (stan)
  63. begin
  64.     case stan is
  65.     when GENERUJ =>
  66.         wave <= '1';
  67.     when CZUWAJ =>
  68.       wave <= '0';
  69.     end case;
  70. end process;
  71.  
  72.  
  73. TIMER_PROC:
  74. process (clk,trig)
  75. begin
  76. if (rising_edge(clk)) then
  77.     if(zeruj='1') then
  78.      stoper <= (others=>'0');
  79. else
  80.         stoper <= stoper + 1;
  81. end if;
  82. end if;
  83. end process;
  84.  
  85.  
  86. SAVE_PULSE_LEN_PROC:
  87. process (clk)
  88. begin
  89.   if(rising_edge(clk) and reset = '0') then
  90.   if(pulse_len = 0) then
  91.   zapisane_pl <= to_unsigned(1,N);
  92.   else
  93.   zapisane_pl <= pulse_len;
  94.   end if;
  95. end if;
  96. end process;
  97.  
  98. end rtl;
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