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  1. CPU: ID 0x30678, Processor Type 0x0, Family 0x6, Model 0x37, Stepping 0x8
  2. Northbridge: 8086:0f00 (Bay Trail)
  3. Southbridge: 8086:0f1c (Bay Trail)
  4. IGD: 8086:0f31 (unknown)
  5.  
  6. ============= GPIOS =============
  7.  
  8. GPIOBASE = 0x0500 (IO)
  9.  
  10. gpiobase+0x0000: 0x00000001 (SC_USE_SEL_31_0_)
  11. gpiobase+0x0004: 0x00000001 (SC_IO_SEL_31_0_)
  12. gpiobase+0x0008: 0x00000001 (SC_GP_LVL_31_0_))
  13. gpiobase+0x000c: 0x00000000 (SC_TPE_31_0_)
  14. gpiobase+0x0010: 0x00000001 (SC_TNE_31_0_)
  15. gpiobase+0x0014: 0x00000000 (SC_TS_31_0_)
  16. gpiobase+0x0020: 0x20800000 (SC_USE_SEL_63_32_)
  17. gpiobase+0x0024: 0x20800000 (SC_IO_SEL_63_32_)
  18. gpiobase+0x0028: 0x20000000 (SC_GP_LVL_63_32_)
  19. gpiobase+0x002c: 0x00000000 (SC_TPE_63_32_)
  20. gpiobase+0x0030: 0x00000000 (SC_TNE_63_32_)
  21. gpiobase+0x0034: 0x00000000 (SC_TS_63_32_)
  22. gpiobase+0x0040: 0x30000000 (SC_USE_SEL_95_64_)
  23. gpiobase+0x0044: 0x30000000 (SC_IO_SEL_95_64_)
  24. gpiobase+0x0048: 0x30000000 (SC_GP_LVL_95_64_)
  25. gpiobase+0x004c: 0x00000000 (SC_TPE_95_64_)
  26. gpiobase+0x0050: 0x00000000 (SC_TNE_95_64_)
  27. gpiobase+0x0054: 0x00000000 (SC_TS_95_64_)
  28. gpiobase+0x0058: 0x00000000 (SC_USE_SEL_127_96_)
  29. gpiobase+0x0064: 0x00000000 (SC_IO_SEL_127_96_)
  30. gpiobase+0x0068: 0x00000000 (SC_GP_LVL_127_96_)
  31. gpiobase+0x006c: 0x00000000 (SC_TPE_127_96_)
  32. gpiobase+0x0070: 0x00000000 (SC_TNE_127_96_)
  33. gpiobase+0x0074: 0x00000000 (SC_TS_127_96_)
  34. gpiobase+0x0080: 0x00000001 (SUS_USE_SEL_31_0_)
  35. gpiobase+0x0084: 0x00000001 (SUS_IO_SEL_31_0_)
  36. gpiobase+0x0088: 0x00000001 (SUS_GP_LVL_31_0_)
  37. gpiobase+0x008c: 0x00000000 (SUS_TPE_31_0_)
  38. gpiobase+0x0090: 0x00000001 (SUS_TNE_31_0_)
  39. gpiobase+0x0094: 0x00000000 (SUS_TS_31_0_)
  40. gpiobase+0x0098: 0x00000081 (SUS_WAKE_EN_31_0_)
  41. gpiobase+0x00a0: 0x00000000 (SUS_USE_SEL_43_32_)
  42. gpiobase+0x00a4: 0x00000000 (SUS_IO_SEL_43_32_)
  43. gpiobase+0x00a8: 0x00000000 (SUS_GP_LVL_43_32_)
  44. gpiobase+0x00ac: 0x00000000 (SUS_TPE_43_32_)
  45. gpiobase+0x00b0: 0x00000000 (SUS_TNE_43_32_)
  46. gpiobase+0x00b4: 0x00000000 (SUS_TS_43_32_)
  47. gpiobase+0x00b8: 0x00000000 (SUS_WAKE_EN_43_32_)
  48.  
  49. IOBASE: 0xfed0c000
  50.  
  51. ========== Bay Trail NCORE GPIOs ===========
  52.  
  53. Address | GPIO # | reg value | Pull Dir & Str | Func #: Func Name | I/O | Current Val
  54. iobase + 0x1130 | GPIO 0 | 0x2003cc82 | Pull: Up 20k | Func 2: DDI0_HPD | Input | Low
  55. iobase + 0x1120 | GPIO 1 | 0x2083cd02 | Pull: Down 20k | Func 2: DDI0_DDCDATA | Input | Low
  56. iobase + 0x1110 | GPIO 2 | 0x2003cc82 | Pull: Up 20k | Func 2: DDI0_DDCCLK | Input | Low
  57. iobase + 0x1140 | GPIO 3 | 0x2003cc00 | Pull: None | Func 0: GPIO_S0_NC[03] | Output / Input | Low
  58. iobase + 0x1150 | GPIO 4 | 0x2003cc00 | Pull: None | Func 0: GPIO_S0_NC[04] | Output / Input | Low
  59. iobase + 0x1160 | GPIO 5 | 0x2003cc00 | Pull: None | Func 0: GPIO_S0_NC[05] | Output / Input | Low
  60. iobase + 0x1180 | GPIO 6 | 0x2003cc82 | Pull: Up 20k | Func 2: DDI1_HPD | Input | Low
  61. iobase + 0x1190 | GPIO 7 | 0x2003cd02 | Pull: Down 20k | Func 2: DDI1_DDCDATA | Input | Low
  62. iobase + 0x1170 | GPIO 8 | 0x2003cc82 | Pull: Up 20k | Func 2: DDI1_DDCCLK | Input | Low
  63. iobase + 0x1100 | GPIO 9 | 0x2003cd02 | Pull: Down 20k | Func 2: DDI1_VDDEN | Input | Low
  64. iobase + 0x10e0 | GPIO 10 | 0x2003cd02 | Pull: Down 20k | Func 2: DDI1_BKLTEN | Input | Low
  65. iobase + 0x10f0 | GPIO 11 | 0x2003cd02 | Pull: Down 20k | Func 2: DDI1_BKLTCTL | Input | Low
  66. iobase + 0x10c0 | GPIO 12 | 0x2003cd01 | Pull: Down 20k | Func 1: RESERVED | Input | Low
  67. iobase + 0x11a0 | GPIO 13 | 0x2003cc00 | Pull: None | Func 0: GPIO_S0_NC[13] | Output / Input | Low
  68. iobase + 0x11b0 | GPIO 14 | 0x2003cc00 | Pull: None | Func 0: GPIO_S0_NC[14] | Output / Input | High
  69. iobase + 0x1010 | GPIO 15 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  70. iobase + 0x1040 | GPIO 16 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  71. iobase + 0x1080 | GPIO 17 | 0x2003cd01 | Pull: Down 20k | Func 1: RESERVED | Input | Low
  72. iobase + 0x10b0 | GPIO 18 | 0x2003cd01 | Pull: Down 20k | Func 1: RESERVED | Input | Low
  73. iobase + 0x1000 | GPIO 19 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  74. iobase + 0x1030 | GPIO 20 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  75. iobase + 0x1060 | GPIO 21 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  76. iobase + 0x10a0 | GPIO 22 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  77. iobase + 0x10d0 | GPIO 23 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  78. iobase + 0x1020 | GPIO 24 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  79. iobase + 0x1050 | GPIO 25 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  80. iobase + 0x1090 | GPIO 26 | 0x2003cc01 | Pull: None | Func 1: RESERVED | Output / Input | Low
  81.  
  82. ========== Bay Trail SCORE GPIOs (GPIO_S0_SC_XX) ===========
  83.  
  84. Address | GPIO # | reg value | Pull Dir & Str | Func #: Func Name | I/O | Current Val
  85. iobase + 0x0550 | GPIO 0 | 0x2203cc00 | Pull: None | Func 0: GPIO_S0_SC[000] | Input | Low
  86. iobase + 0x0590 | GPIO 1 | 0x2003cd02 | Pull: Down 20k | Func 2: SATA_DEVSLP[0] | Input | Low
  87. iobase + 0x05d0 | GPIO 2 | 0x2603cc81 | Pull: Up 20k | Func 1: SATA_LED# | Input | Low
  88. iobase + 0x0600 | GPIO 3 | 0x2003cc81 | Pull: Up 20k | Func 1: PCIE_CLKREQ[0]# | Input | High
  89. iobase + 0x0630 | GPIO 4 | 0x2603cc81 | Pull: Up 20k | Func 1: PCIE_CLKREQ[1]# | Input | High
  90. iobase + 0x0660 | GPIO 5 | 0x2603cc81 | Pull: Up 20k | Func 1: PCIE_CLKREQ[2]# | Input | High
  91. iobase + 0x0620 | GPIO 6 | 0x2603cc81 | Pull: Up 20k | Func 1: PCIE_CLKREQ[3]# | Input | High
  92. iobase + 0x0650 | GPIO 7 | 0x2603cc80 | Pull: Up 20k | Func 0: GPIO_S0_SC[007] | Input | High
  93. iobase + 0x0220 | GPIO 8 | 0x2003ed02 | Pull: Down 20k | Func 2: HDA_RST# | Input | High
  94. iobase + 0x0250 | GPIO 9 | 0x2003ed02 | Pull: Down 20k | Func 2: HDA_SYNC | Input | Low
  95. iobase + 0x0240 | GPIO 10 | 0x2003ed02 | Pull: Down 20k | Func 2: HDA_CLK | Input | Low
  96. iobase + 0x0260 | GPIO 11 | 0x2003ed02 | Pull: Down 20k | Func 2: HDA_SDO | Input | Low
  97. iobase + 0x0270 | GPIO 12 | 0x2003ed02 | Pull: Down 20k | Func 2: HDA_SDI[0] | Input | Low
  98. iobase + 0x0230 | GPIO 13 | 0x2003ed02 | Pull: Down 20k | Func 2: HDA_SDI[1] | Input | Low
  99. iobase + 0x0280 | GPIO 14 | 0x2003ed02 | Pull: Down 20k | Func 2: RESERVED | Input | High
  100. iobase + 0x0540 | GPIO 15 | 0x2003cd02 | Pull: Down 20k | Func 2: RESERVED | Input | High
  101. iobase + 0x03e0 | GPIO 16 | 0x2003ed01 | Pull: Down 20k | Func 1: MMC1_CLK | Input | Low
  102. iobase + 0x03d0 | GPIO 17 | 0x2003ec81 | Pull: Up 20k | Func 1: MMC1_D[0] | Input | Low
  103. iobase + 0x0400 | GPIO 18 | 0x2003ec81 | Pull: Up 20k | Func 1: MMC1_D[1] | Input | Low
  104. iobase + 0x03b0 | GPIO 19 | 0x2003ec81 | Pull: Up 20k | Func 1: MMC1_D[2] | Input | Low
  105. iobase + 0x0360 | GPIO 20 | 0x2003ec81 | Pull: Up 20k | Func 1: MMC1_D[3] | Input | High
  106. iobase + 0x0380 | GPIO 21 | 0x2003ec81 | Pull: Up 20k | Func 1: MMC1_D[4] | Input | Low
  107. iobase + 0x03c0 | GPIO 22 | 0x2003ec81 | Pull: Up 20k | Func 1: MMC1_D[5] | Input | Low
  108. iobase + 0x0370 | GPIO 23 | 0x2003ec81 | Pull: Up 20k | Func 1: MMC1_D[6] | Input | Low
  109. iobase + 0x03f0 | GPIO 24 | 0x2003ec81 | Pull: Up 20k | Func 1: MMC1_D[7] | Input | Low
  110. iobase + 0x0390 | GPIO 25 | 0x2003ec81 | Pull: Up 20k | Func 1: MMC1_CMD | Input | Low
  111. iobase + 0x0330 | GPIO 26 | 0x2003ed01 | Pull: Down 20k | Func 1: MMC1_RST# | Input | High
  112. iobase + 0x0320 | GPIO 27 | 0x2003ed01 | Pull: Down 20k | Func 1: SD2_CLK | Input | Low
  113. iobase + 0x0350 | GPIO 28 | 0x2003ec81 | Pull: Up 20k | Func 1: SD2_D[0] | Input | Low
  114. iobase + 0x02f0 | GPIO 29 | 0x2003ec81 | Pull: Up 20k | Func 1: SD2_D[1] | Input | Low
  115. iobase + 0x0340 | GPIO 30 | 0x2003ec81 | Pull: Up 20k | Func 1: SD2_D[2] | Input | Low
  116. iobase + 0x0310 | GPIO 31 | 0x2003ec81 | Pull: Up 20k | Func 1: SD2_D[3]_CD# | Input | High
  117. iobase + 0x0300 | GPIO 32 | 0x2003ec81 | Pull: Up 20k | Func 1: SD2_CMD | Input | Low
  118. iobase + 0x02b0 | GPIO 33 | 0x20038d01 | Pull: Down 20k | Func 1: SD3_CLK | Input | Low
  119. iobase + 0x02e0 | GPIO 34 | 0x20038c81 | Pull: Up 20k | Func 1: SD3_D[0] | Input | Low
  120. iobase + 0x0290 | GPIO 35 | 0x20038c81 | Pull: Up 20k | Func 1: SD3_D[1] | Input | Low
  121. iobase + 0x02d0 | GPIO 36 | 0x20038c81 | Pull: Up 20k | Func 1: SD3_D[2] | Input | Low
  122. iobase + 0x02a0 | GPIO 37 | 0x20038c81 | Pull: Up 20k | Func 1: SD3_D[3] | Input | Low
  123. iobase + 0x03a0 | GPIO 38 | 0x2003cc81 | Pull: Up 20k | Func 1: SD3_CD# | Input | High
  124. iobase + 0x02c0 | GPIO 39 | 0x20038c81 | Pull: Up 20k | Func 1: SD3_CMD | Input | Low
  125. iobase + 0x05f0 | GPIO 40 | 0x2003cd01 | Pull: Down 20k | Func 1: SD3_1P8EN | Input | Low
  126. iobase + 0x0690 | GPIO 41 | 0x2003cc81 | Pull: Up 20k | Func 1: SD3_PWREN# | Input | High
  127. iobase + 0x0460 | GPIO 42 | 0x20038c81 | Pull: Up 20k | Func 1: ILB_LPC_AD[0] | Input | Low
  128. iobase + 0x0440 | GPIO 43 | 0x20038c81 | Pull: Up 20k | Func 1: ILB_LPC_AD[1] | Input | Low
  129. iobase + 0x0430 | GPIO 44 | 0x20038c81 | Pull: Up 20k | Func 1: ILB_LPC_AD[2] | Input | Low
  130. iobase + 0x0420 | GPIO 45 | 0x20038c81 | Pull: Up 20k | Func 1: ILB_LPC_AD[3] | Input | Low
  131. iobase + 0x0450 | GPIO 46 | 0x20038c81 | Pull: Up 20k | Func 1: ILB_LPC_FRAME# | Input | High
  132. iobase + 0x0470 | GPIO 47 | 0x20038d01 | Pull: Down 20k | Func 1: ILB_LPC_CLK[0] | Input | Low
  133. iobase + 0x0410 | GPIO 48 | 0x20038d01 | Pull: Down 20k | Func 1: ILB_LPC_CLK[1] | Input | Low
  134. iobase + 0x0480 | GPIO 49 | 0x20038c81 | Pull: Up 20k | Func 1: ILB_LPC_CLKRUN# | Input | High
  135. iobase + 0x0560 | GPIO 50 | 0x2003cc81 | Pull: Up 20k | Func 1: ILB_LPC_SERIRQ | Input | Low
  136. iobase + 0x05a0 | GPIO 51 | 0x2003cc81 | Pull: Up 20k | Func 1: PCU_SMB_DATA | Input | Low
  137. iobase + 0x0580 | GPIO 52 | 0x2003cc81 | Pull: Up 20k | Func 1: PCU_SMB_CLK | Input | Low
  138. iobase + 0x05c0 | GPIO 53 | 0x2003cc81 | Pull: Up 20k | Func 1: PCU_SMB_ALERT# | Input | High
  139. iobase + 0x0670 | GPIO 54 | 0x2003cd01 | Pull: Down 20k | Func 1: ILB_8254_SPKR | Input | Low
  140. iobase + 0x04d0 | GPIO 55 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S0_SC[055] | Input | Low
  141. iobase + 0x04f0 | GPIO 56 | 0x2083cd01 | Pull: Down 20k | Func 1: RESERVED | Output / Input | Low
  142. iobase + 0x0530 | GPIO 57 | 0x2003cc81 | Pull: Up 20k | Func 1: PCU_UART_TXD | Input | Low
  143. iobase + 0x04e0 | GPIO 58 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S0_SC[058] | Input | Low
  144. iobase + 0x0510 | GPIO 59 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S0_SC[059] | Output / Input | Low
  145. iobase + 0x0500 | GPIO 60 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S0_SC[060] | Output / Input | Low
  146. iobase + 0x0520 | GPIO 61 | 0x2003cc80 | Pull: Up 20k | Func 0: GPIO_S0_SC[061] | Input | Low
  147. iobase + 0x00d0 | GPIO 62 | 0x2003cd01 | Pull: Down 20k | Func 1: LPE_I2S2_CLK | Input | Low
  148. iobase + 0x00c0 | GPIO 63 | 0x2083cd01 | Pull: Down 20k | Func 1: LPE_I2S2_FRM | Input | Low
  149. iobase + 0x00f0 | GPIO 64 | 0x2003cd01 | Pull: Down 20k | Func 1: LPE_I2S2_DATAIN | Input | Low
  150. iobase + 0x00e0 | GPIO 65 | 0x2083cd01 | Pull: Down 20k | Func 1: LPE_I2S2_DATAOUT | Input | Low
  151. iobase + 0x0110 | GPIO 66 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_SPI_CS# | Input | High
  152. iobase + 0x0120 | GPIO 67 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_SPI_MISO | Input | Low
  153. iobase + 0x0130 | GPIO 68 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_SPI_MOSI | Input | Low
  154. iobase + 0x0100 | GPIO 69 | 0x2003cd01 | Pull: Down 20k | Func 1: SIO_SPI_CLK | Input | Low
  155. iobase + 0x0020 | GPIO 70 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_UART1_RXD | Input | Low
  156. iobase + 0x0010 | GPIO 71 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_UART1_TXD | Input | Low
  157. iobase + 0x0000 | GPIO 72 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_UART1_RTS# | Input | High
  158. iobase + 0x0040 | GPIO 73 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_UART1_CTS# | Input | High
  159. iobase + 0x0060 | GPIO 74 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_UART2_RXD | Input | Low
  160. iobase + 0x0070 | GPIO 75 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_UART2_TXD | Input | Low
  161. iobase + 0x0090 | GPIO 76 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_UART2_RTS# | Input | High
  162. iobase + 0x0080 | GPIO 77 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_UART2_CTS# | Input | High
  163. iobase + 0x0210 | GPIO 78 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C0_DATA | Input | Low
  164. iobase + 0x0200 | GPIO 79 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C0_CLK | Input | Low
  165. iobase + 0x01f0 | GPIO 80 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C1_DATA | Input | Low
  166. iobase + 0x01e0 | GPIO 81 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C1_CLK | Input | Low
  167. iobase + 0x01d0 | GPIO 82 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C2_DATA | Input | Low
  168. iobase + 0x01b0 | GPIO 83 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C2_CLK | Input | Low
  169. iobase + 0x0190 | GPIO 84 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C3_DATA | Input | Low
  170. iobase + 0x01c0 | GPIO 85 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C3_CLK | Input | Low
  171. iobase + 0x01a0 | GPIO 86 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C4_DATA | Input | Low
  172. iobase + 0x0170 | GPIO 87 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C4_CLK | Input | Low
  173. iobase + 0x0150 | GPIO 88 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C5_DATA | Input | Low
  174. iobase + 0x0140 | GPIO 89 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C5_CLK | Input | Low
  175. iobase + 0x0180 | GPIO 90 | 0x2003cc81 | Pull: Up 20k | Func 1: SIO_I2C6_DATA | Input | Low
  176. iobase + 0x0160 | GPIO 91 | 0x2003cc82 | Pull: Up 20k | Func 2: SD3_WP | Input | Low
  177. iobase + 0x0050 | GPIO 92 | 0x2003cc81 | Pull: Up 20k | Func 1: GPIO_S0_SC[092] | Input | Low
  178. iobase + 0x0030 | GPIO 93 | 0x2003cc81 | Pull: Up 20k | Func 1: GPIO_S0_SC[093] | Input | Low
  179. iobase + 0x00a0 | GPIO 94 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S0_SC[094] | Input | Low
  180. iobase + 0x00b0 | GPIO 95 | 0x2003cc00 | Pull: None | Func 0: GPIO_S0_SC[095] | Output / Input | Low
  181. iobase + 0x06a0 | GPIO 96 | 0x2003cd01 | Pull: Down 20k | Func 1: PMC_PLT_CLK[0] | Input | Low
  182. iobase + 0x0570 | GPIO 97 | 0x2003cd01 | Pull: Down 20k | Func 1: PMC_PLT_CLK[1] | Input | Low
  183. iobase + 0x05b0 | GPIO 98 | 0x2003cd01 | Pull: Down 20k | Func 1: PMC_PLT_CLK[2] | Input | Low
  184. iobase + 0x0680 | GPIO 99 | 0x2003cd01 | Pull: Down 20k | Func 1: PMC_PLT_CLK[3] | Input | Low
  185. iobase + 0x0610 | GPIO 100 | 0x2003cd01 | Pull: Down 20k | Func 1: PMC_PLT_CLK[4] | Input | Low
  186. iobase + 0x0640 | GPIO 101 | 0x2003cd01 | Pull: Down 20k | Func 1: PMC_PLT_CLK[5] | Input | Low
  187.  
  188. ========== Bay Trail SSUS GPIOs (GPIO_S5) ===========
  189.  
  190. Address | GPIO # | reg value | Pull Dir & Str | Func #: Func Name | I/O | Current Val
  191. iobase + 0x21d0 | GPIO 0 | 0x2303cc80 | Pull: Up 20k | Func 0: GPIO_S5[00] | Input | Low
  192. iobase + 0x2210 | GPIO 1 | 0x2003cd01 | Pull: Down 20k | Func 1: RESERVED | Input | Low
  193. iobase + 0x21e0 | GPIO 2 | 0x2003cc86 | Pull: Up 20k | Func 6: PMC_WAKE_PCIE[2]# | Input | Low
  194. iobase + 0x21f0 | GPIO 3 | 0x2003cc80 | Pull: Up 20k | Func 0: GPIO_S5[03] | Input | High
  195. iobase + 0x2200 | GPIO 4 | 0x2203cd00 | Pull: Down 20k | Func 0: GPIO_S5[04] | Input | Low
  196. iobase + 0x2220 | GPIO 5 | 0x2003cd01 | Pull: Down 20k | Func 1: PMC_SUSCLK[1] | Input | Low
  197. iobase + 0x2240 | GPIO 6 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S5[06] | Input | Low
  198. iobase + 0x2230 | GPIO 7 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S5[07] | Output / Input | Low
  199. iobase + 0x2260 | GPIO 8 | 0x2303cc00 | Pull: None | Func 0: GPIO_S5[08] | Output / Input | Low
  200. iobase + 0x2250 | GPIO 9 | 0x2003cc00 | Pull: None | Func 0: GPIO_S5[09] | Output / Input | Low
  201. iobase + 0x2120 | GPIO 10 | 0x2c03cc80 | Pull: Up 20k | Func 0: GPIO_S5[10] | Input | High
  202. iobase + 0x2070 | GPIO 11 | 0x2003cd00 | Pull: Down 20k | Func 0: PMC_SUSPWRDNACK | Input | Low
  203. iobase + 0x20b0 | GPIO 12 | 0x2003cd00 | Pull: Down 20k | Func 0: PMC_SUSCLK[0] | Input | High
  204. iobase + 0x2140 | GPIO 13 | 0x2003cd00 | Pull: Down 20k | Func 0: RESERVED | Input | High
  205. iobase + 0x2110 | GPIO 14 | 0x2003cc02 | Pull: None | Func 2: USB_ULPI_RST# | Output / Input | High
  206. iobase + 0x2010 | GPIO 15 | 0x2303cc80 | Pull: Up 20k | Func 0: PMC_WAKE_PCIE[0]# | Input | High
  207. iobase + 0x2080 | GPIO 16 | 0x2003cc80 | Pull: Up 20k | Func 0: PMC_PWRBTN# | Input | High
  208. iobase + 0x20a0 | GPIO 17 | 0x2303cc81 | Pull: Up 20k | Func 1: GPIO_S5[17] | Input | High
  209. iobase + 0x2130 | GPIO 18 | 0x2003cd00 | Pull: Down 20k | Func 0: PMC_SUS_STAT# | Input | High
  210. iobase + 0x20c0 | GPIO 19 | 0x2003cc81 | Pull: Up 20k | Func 1: GPIO_S5[19] | Input | High
  211. iobase + 0x2000 | GPIO 20 | 0x2003cc81 | Pull: Up 20k | Func 1: GPIO_S5[20] | Input | High
  212. iobase + 0x2020 | GPIO 21 | 0x2003ec81 | Pull: Up 20k | Func 1: GPIO_S5[21] | Input | High
  213. iobase + 0x2170 | GPIO 22 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S5[22] | Output | Low
  214. iobase + 0x2270 | GPIO 23 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S5[23] | Input | Low
  215. iobase + 0x21c0 | GPIO 24 | 0x2503cd00 | Pull: Down 20k | Func 0: GPIO_S5[24] | Output / Input | Low
  216. iobase + 0x21b0 | GPIO 25 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S5[25] | Output / Input | Low
  217. iobase + 0x2160 | GPIO 26 | 0x2003cd00 | Pull: Down 20k | Func 0: GPIO_S5[26] | Input | Low
  218. iobase + 0x2150 | GPIO 27 | 0x2603cc80 | Pull: Up 20k | Func 0: GPIO_S5[27] | Input | Low
  219. iobase + 0x2180 | GPIO 28 | 0x2603cc82 | Pull: Up 20k | Func 2: RESERVED | Input | Low
  220. iobase + 0x2190 | GPIO 29 | 0x2003cc00 | Pull: None | Func 0: GPIO_S5[29] | Output / Input | Low
  221. iobase + 0x21a0 | GPIO 30 | 0x2003cc00 | Pull: None | Func 0: GPIO_S5[30] | Output / Input | Low
  222. iobase + 0x2330 | GPIO 31 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_CLK | Input | Low
  223. iobase + 0x2380 | GPIO 32 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_DATA[0] | Input | Low
  224. iobase + 0x2360 | GPIO 33 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_DATA[1] | Input | Low
  225. iobase + 0x2310 | GPIO 34 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_DATA[2] | Input | Low
  226. iobase + 0x2370 | GPIO 35 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_DATA[3] | Input | Low
  227. iobase + 0x2300 | GPIO 36 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_DATA[4] | Input | Low
  228. iobase + 0x2390 | GPIO 37 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_DATA[5] | Input | Low
  229. iobase + 0x2320 | GPIO 38 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_DATA[6] | Input | Low
  230. iobase + 0x23a0 | GPIO 39 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_DATA[7] | Input | Low
  231. iobase + 0x2340 | GPIO 40 | 0x2003cc01 | Pull: None | Func 1: USB_ULPI_DIR | Output / Input | Low
  232. iobase + 0x2350 | GPIO 41 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_NXT | Input | Low
  233. iobase + 0x23b0 | GPIO 42 | 0x2003cc81 | Pull: Up 20k | Func 1: USB_ULPI_STP | Input | Low
  234. iobase + 0x2280 | GPIO 43 | 0x2003cd01 | Pull: Down 20k | Func 1: USB_ULPI_REFCLK | Input | Low
  235.  
  236.  
  237.  
  238. ============= RCBA ==============
  239.  
  240. Error: Dumping RCBA on this southbridge is not (yet) supported.
  241.  
  242.  
  243.  
  244. ========== PMBASE/ABASE =========
  245.  
  246. PMBASE = 0x0400 (IO)
  247.  
  248. pmbase+0x0000: 0x2001 (PM1_STS)
  249. pmbase+0x0002: 0x0120 (PM1_EN)
  250. pmbase+0x0004: 0x00000001 (PM1_CNT)
  251. pmbase+0x0008: 0x0002b806 (PM1_TMR)
  252. pmbase+0x000c: 0x00000000 (RESERVED)
  253. pmbase+0x0010: 0x00000000 (RESERVED)
  254. pmbase+0x0014: 0x00000000 (RESERVED)
  255. pmbase+0x0018: 0x00000000 (RESERVED)
  256. pmbase+0x001c: 0x00000000 (RESERVED)
  257. pmbase+0x0020: 0x00000000 (GPE0_STS)
  258. 0x00000000
  259. pmbase+0x0028: 0x02810006 (GPE0_EN)
  260. 0x00000000
  261. pmbase+0x0030: 0x00020033 (SMI_EN)
  262. pmbase+0x0034: 0x00004100 (SMI_STS)
  263. pmbase+0x0038: 0x0000 (ALT_GP_SMI_EN)
  264. pmbase+0x003a: 0x0000 (ALT_GP_SMI_STS)
  265. pmbase+0x003c: 0x00 (UPRWC)
  266. pmbase+0x003d: 0x01 (RESERVED)
  267. pmbase+0x003e: 0x0000 (RESERVED)
  268. pmbase+0x0040: 0x0000 (RESERVED)
  269. pmbase+0x0042: 0x00 (GPE_CNTL)
  270. pmbase+0x0043: 0x00 (RESERVED)
  271. pmbase+0x0044: 0x0000 (DEVACT_STS)
  272. pmbase+0x0046: 0x0000 (RESERVED)
  273. pmbase+0x0048: 0x00000000 (RESERVED)
  274. pmbase+0x004c: 0x00000000 (RESERVED)
  275. pmbase+0x0050: 0x00 (PM2_CNT)
  276. pmbase+0x0051: 0x00 (RESERVED)
  277. pmbase+0x0052: 0x0000 (RESERVED)
  278. pmbase+0x0054: 0x00000000 (RESERVED)
  279. pmbase+0x0058: 0x00000000 (RESERVED)
  280. pmbase+0x005c: 0x00000000 (RESERVED)
  281. pmbase+0x0060: 0x0004 (TCO_RLD)
  282. pmbase+0x0062: 0x00 (TCO_DAT_IN)
  283. pmbase+0x0063: 0x00 (TCO_DAT_OUT)
  284. pmbase+0x0064: 0x0000 (TCO1_STS)
  285. pmbase+0x0066: 0x0000 (TCO2_STS)
  286. pmbase+0x0068: 0x0800 (TCO1_CNT)
  287. pmbase+0x006a: 0x0000 (TCO2_CNT)
  288. pmbase+0x006c: 0x0000 (TCO_MESSAGE)
  289. pmbase+0x006e: 0x00 (TCO_WDCNT)
  290. pmbase+0x006f: 0x00 (RESERVED)
  291. pmbase+0x0070: 0x00 (SW_IRQ_GEN)
  292. pmbase+0x0071: 0x00 (RESERVED)
  293. pmbase+0x0072: 0x001e (TCO_TMR)
  294. pmbase+0x0074: 0x00000000 (RESERVED)
  295. pmbase+0x0078: 0x00000000 (RESERVED)
  296. pmbase+0x007c: 0x00000000 (RESERVED)
  297.  
  298.  
  299.  
  300. ============= MCHBAR ============
  301.  
  302. Error: Dumping MCHBAR on this northbridge is not (yet) supported.
  303.  
  304.  
  305.  
  306. ============= EPBAR =============
  307.  
  308. Error: Dumping EPBAR on this northbridge is not (yet) supported.
  309.  
  310.  
  311.  
  312. ============= DMIBAR ============
  313.  
  314. Error: Dumping DMIBAR on this northbridge is not (yet) supported.
  315.  
  316.  
  317. ========= PCIEXBAR ========
  318.  
  319. Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.
  320.  
  321.  
  322.  
  323. ===================== SHARED MSRs (All Cores) =====================
  324. MSR 0x00000000 = 0x00000000:0x00000000 (IA32_P5_MC_ADDR)
  325. MSR 0x00000001 = 0x00000000:0x00000000 (IA32_P5_MC_TYPE)
  326. MSR 0x00000017 = 0x00080000:0x90241D4A (IA32_PLATFORM_ID)
  327. MSR 0x0000002A = 0x00000000:0x40080000 (MSR_EBC_HARD_POWERON)
  328. MSR 0x000000CD = 0x00000000:0x00000000 (MSR_FSB_FREQ)
  329. MSR 0x000000E2 = 0x00000000:0x0018000F (MSR_PKG_CST_CONFIG_CONTROL)
  330. MSR 0x000000E4 = 0x00000000:0x00020000 (MSR_PMG_IO_CAPTURE_BASE)
  331. MSR 0x0000011E = 0x00000000:0x7E2801FF (BBL_CR_CTL3)
  332. MSR 0x00000198 = 0x00007E00:0x0000102F (IA32_PERF_STATUS)
  333. MSR 0x000001A2 = 0x00000000:0x00690000 (MSR_TEMPERATURE_TARGET)
  334. MSR 0x000001A6 = 0x00000000:0x00000000 (MSR_OFFCORE_RSP_0)
  335. MSR 0x000001A7 = 0x00000000:0x00000000 (MSR_OFFCORE_RSP_1)
  336. MSR 0x000001AD = 0x00000000:0x00000000 (MSR_TURBO_RATIO_LIMIT)
  337. MSR 0x000003FA = 0x000000EA:0x15DA84A0 (MSR_PKG_C6_RESIDENCY)
  338. MSR 0x00000400 = 0x00000000:0x0000003F (IA32_MC0_CTL)
  339. MSR 0x00000401 = 0x00000000:0x00000000 (IA32_MC0_STATUS)
  340. MSR 0x00000402 = 0x00000000:0x00000000 (IA32_MC0_ADDR)
  341. MSR 0x00000404 = 0x00000000:0x00000001 (IA32_MC1_CTL)
  342. MSR 0x00000405 = 0x00000000:0x00000000 (IA32_MC1_STATUS)
  343. MSR 0x00000408 = 0x00000000:0x00000003 (IA32_MC2_CTL)
  344. MSR 0x00000409 = 0x00000000:0x00000000 (IA32_MC2_STATUS)
  345. MSR 0x0000040A = 0x00000000:0x00000000 (IA32_MC2_ADDR)
  346. MSR 0x00000414 = 0x00000000:0x00000007 (MSR_MC5_CTL)
  347. MSR 0x00000415 = 0x00000000:0x00000000 (MSR_MC5_STATUS)
  348. MSR 0x00000416 = 0x00000000:0x00000000 (MSR_MC5_ADDR)
  349.  
  350. ====================== UNIQUE MSRs (core 0) ======================
  351. MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE)
  352. MSR 0x00000010 = 0x000001B0:0x2A93A710 (IA32_TIME_STAMP_COUNTER)
  353. MSR 0x0000001B = 0x00000000:0xFEE00900 (IA32_APIC_BASE)
  354. MSR 0x00000034 = 0x00000000:0x00004CDC (MSR_SMI_COUNT)
  355. MSR 0x0000003A = 0x00000000:0x00000005 (IA32_FEATURE_CONTROL)
  356. MSR 0x00000040 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_FROM_IP)
  357. MSR 0x00000041 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_FROM_IP)
  358. MSR 0x00000042 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_FROM_IP)
  359. MSR 0x00000043 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_FROM_IP)
  360. MSR 0x00000044 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_FROM_IP)
  361. MSR 0x00000045 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_FROM_IP)
  362. MSR 0x00000046 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_FROM_IP)
  363. MSR 0x00000047 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_FROM_IP)
  364. MSR 0x00000060 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_TO_IP)
  365. MSR 0x00000061 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_TO_IP)
  366. MSR 0x00000062 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_TO_IP)
  367. MSR 0x00000063 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_TO_IP)
  368. MSR 0x00000064 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_TO_IP)
  369. MSR 0x00000065 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_TO_IP)
  370. MSR 0x00000066 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_TO_IP)
  371. MSR 0x00000067 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_TO_IP)
  372. MSR 0x0000008B = 0x00000838:0x00000000 (IA32_BIOS_SIGN_ID)
  373. MSR 0x000000C1 = 0x00000000:0x00000000 (IA32_PMC0)
  374. MSR 0x000000C2 = 0x00000000:0x0000FFFF (IA32_PMC1)
  375. MSR 0x000000E7 = 0x00000082:0x4A4361E8 (IA32_MPERF)
  376. MSR 0x000000E8 = 0x00000083:0x070B13F6 (IA32_APERF)
  377. MSR 0x000000FE = 0x00000000:0x00000D08 (IA32_MTRRCAP)
  378. MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS)
  379. MSR 0x00000175 = 0xFFFFFE00:0x00002200 (IA32_SYSENTER_ESP)
  380. MSR 0x00000176 = 0xFFFFFFFF:0xB3C01790 (IA32_SYSENTER_EIP)
  381. MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP)
  382. MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
  383. MSR 0x00000186 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL0)
  384. MSR 0x00000187 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL1)
  385. MSR 0x00000199 = 0x00000000:0x0000102F (IA32_PERF_CONTROL)
  386. MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION)
  387. MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT)
  388. MSR 0x0000019C = 0x00000000:0x88430000 (IA32_THERM_STATUS)
  389. MSR 0x000001A0 = 0x00000000:0x00850089 (IA32_MISC_ENABLES)
  390. MSR 0x000001B0 = 0x00000000:0x00000006 (IA32_ENERGY_PERF_BIAS)
  391. MSR 0x000001C9 = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS)
  392. MSR 0x000001D9 = 0x00000000:0x00000000 (IA32_DEBUGCTL)
  393. MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LER_FROM_LIP)
  394. MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LER_TO_LIP)
  395. MSR 0x000001F2 = 0x00000000:0xBA000006 (IA32_SMRR_PHYSBASE)
  396. MSR 0x000001F3 = 0x00000000:0xFF800800 (IA32_SMRR_PHYSMASK)
  397. MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0)
  398. MSR 0x00000201 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK0)
  399. MSR 0x00000202 = 0x00000000:0x80000006 (IA32_MTRR_PHYSBASE1)
  400. MSR 0x00000203 = 0x0000000F:0xC0000800 (IA32_MTRR_PHYSMASK1)
  401. MSR 0x00000204 = 0x00000000:0xBA000000 (IA32_MTRR_PHYSBASE2)
  402. MSR 0x00000205 = 0x0000000F:0xFE000800 (IA32_MTRR_PHYSMASK2)
  403. MSR 0x00000206 = 0x00000000:0xBC000000 (IA32_MTRR_PHYSBASE3)
  404. MSR 0x00000207 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK3)
  405. MSR 0x00000208 = 0x00000001:0x00000006 (IA32_MTRR_PHYSBASE4)
  406. MSR 0x00000209 = 0x0000000F:0x00000800 (IA32_MTRR_PHYSMASK4)
  407. MSR 0x0000020A = 0x00000002:0x00000006 (IA32_MTRR_PHYSBASE5)
  408. MSR 0x0000020B = 0x0000000E:0x00000800 (IA32_MTRR_PHYSMASK5)
  409. MSR 0x0000020C = 0x00000004:0x00000006 (IA32_MTRR_PHYSBASE6)
  410. MSR 0x0000020D = 0x0000000F:0xC0000800 (IA32_MTRR_PHYSMASK6)
  411. MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7)
  412. MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7)
  413. MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000)
  414. MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000)
  415. MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000)
  416. MSR 0x00000268 = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_C0000)
  417. MSR 0x00000269 = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_C8000)
  418. MSR 0x0000026A = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_D0000)
  419. MSR 0x0000026B = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_D8000)
  420. MSR 0x0000026C = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E0000)
  421. MSR 0x0000026D = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_E8000)
  422. MSR 0x0000026E = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F0000)
  423. MSR 0x0000026F = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F8000)
  424. MSR 0x00000277 = 0x04070506:0x00070106 (IA32_PAT)
  425. MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE)
  426. MSR 0x00000309 = 0x00000000:0x00000000 (IA32_FIXED_CTR0)
  427. MSR 0x0000030A = 0x000000FC:0xD2CAE868 (IA32_FIXED_CTR1)
  428. MSR 0x0000030B = 0x00000000:0x00000000 (IA32_FIXED_CTR2)
  429. MSR 0x00000345 = 0x00000000:0x000032C1 (IA32_PERF_CAPABILITIES)
  430. MSR 0x0000038D = 0x00000000:0x000000B0 (IA32_FIXED_CTR_CTRL)
  431. MSR 0x0000038E = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_STATUS)
  432. MSR 0x0000038F = 0x00000007:0x00000003 (IA32_PERF_GLOBAL_CTRL)
  433. MSR 0x00000390 = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_OVF_CTRL)
  434. MSR 0x000003F1 = 0x00000000:0x00000000 (MSR_PEBS_ENABLE)
  435. MSR 0x000003FD = 0x0000010F:0xCA496A80 (MSR_CORE_C6_RESIDENCY)
  436. MSR 0x0000040C = 0x00000000:0x00000003 (IA32_MC3_CTL)
  437. MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS)
  438. MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR)
  439. MSR 0x00000410 = 0x00000000:0x00000001 (IA32_MC4_CTL)
  440. MSR 0x00000411 = 0x00000000:0x00000000 (IA32_MC4_STATUS)
  441. MSR 0x00000412 = 0x00000000:0x00000000 (IA32_MC4_ADDR)
  442. MSR 0x00000480 = 0x00DA0400:0x00000002 (IA32_VMX_BASIC)
  443. MSR 0x00000481 = 0x0000007F:0x00000016 (IA32_VMX_PINBASED_CTLS)
  444. MSR 0x00000482 = 0xFFF9FFFE:0x0401E172 (IA32_VMX_PROCBASED_CTLS)
  445. MSR 0x00000483 = 0x007FFFFF:0x00036DFF (IA32_VMX_EXIT_CTLS)
  446. MSR 0x00000484 = 0x0000FFFF:0x000011FF (IA32_VMX_ENTRY_CTLS)
  447. MSR 0x00000485 = 0x00000000:0x000481E6 (IA32_VMX_MISC)
  448. MSR 0x00000486 = 0x00000000:0x80000021 (IA32_VMX_CR0_FIXED0)
  449. MSR 0x00000487 = 0x00000000:0xFFFFFFFF (IA32_VMX_CR0_FIXED1)
  450. MSR 0x00000488 = 0x00000000:0x00002000 (IA32_VMX_CR4_FIXED0)
  451. MSR 0x00000489 = 0x00000000:0x001027FF (IA32_VMX_CR4_FIXED1)
  452. MSR 0x0000048A = 0x00000000:0x0000002E (IA32_VMX_VMCS_ENUM)
  453. MSR 0x0000048B = 0x000028EF:0x00000000 (IA32_VMX_PROCBASED_CTLS2)
  454. MSR 0x0000048C = 0x00000F01:0x06114141 (IA32_VMX_EPT_VPID_ENUM)
  455. MSR 0x0000048D = 0x0000007F:0x00000016 (IA32_VMX_TRUE_PINBASED_CTLS)
  456. MSR 0x0000048E = 0xFFF9FFFE:0x04006172 (IA32_VMX_TRUE_PROCBASED_CTLS)
  457. MSR 0x0000048F = 0x007FFFFF:0x00036DFB (IA32_VMX_TRUE_EXIT_CTLS)
  458. MSR 0x00000490 = 0x0000FFFF:0x000011FB (IA32_VMX_TRUE_ENTRY_CTLS)
  459. MSR 0x00000491 = 0x00000000:0x00000001 (IA32_VMX_FMFUNC)
  460. MSR 0x000004C1 = 0x00000000:0x00000000 (IA32_A_PMC0)
  461. MSR 0x000004C2 = 0x00000000:0x0000FFFF (IA32_A_PMC1)
  462. MSR 0x00000600 = 0xFFFFFE00:0x00013000 (IA32_DS_AREA)
  463. MSR 0x00000660 = 0x00000003:0xDF7B4C10 (MSR_CORE_C1_RESIDENCY)
  464. MSR 0x000006E0 = 0x000001B0:0x2AC04F18 (IA32_TSC_DEADLINE)
  465.  
  466. ====================== UNIQUE MSRs (core 1) ======================
  467. MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE)
  468. MSR 0x00000010 = 0x000001B0:0x2ABB4178 (IA32_TIME_STAMP_COUNTER)
  469. MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE)
  470. MSR 0x00000034 = 0x00000000:0x00004CDC (MSR_SMI_COUNT)
  471. MSR 0x0000003A = 0x00000000:0x00000005 (IA32_FEATURE_CONTROL)
  472. MSR 0x00000040 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_FROM_IP)
  473. MSR 0x00000041 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_FROM_IP)
  474. MSR 0x00000042 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_FROM_IP)
  475. MSR 0x00000043 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_FROM_IP)
  476. MSR 0x00000044 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_FROM_IP)
  477. MSR 0x00000045 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_FROM_IP)
  478. MSR 0x00000046 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_FROM_IP)
  479. MSR 0x00000047 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_FROM_IP)
  480. MSR 0x00000060 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_TO_IP)
  481. MSR 0x00000061 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_TO_IP)
  482. MSR 0x00000062 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_TO_IP)
  483. MSR 0x00000063 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_TO_IP)
  484. MSR 0x00000064 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_TO_IP)
  485. MSR 0x00000065 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_TO_IP)
  486. MSR 0x00000066 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_TO_IP)
  487. MSR 0x00000067 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_TO_IP)
  488. MSR 0x0000008B = 0x00000838:0x00000000 (IA32_BIOS_SIGN_ID)
  489. MSR 0x000000C1 = 0x00000000:0x00000000 (IA32_PMC0)
  490. MSR 0x000000C2 = 0x00000000:0x00000000 (IA32_PMC1)
  491. MSR 0x000000E7 = 0x00000016:0xBD302C78 (IA32_MPERF)
  492. MSR 0x000000E8 = 0x00000018:0x5F1D36C0 (IA32_APERF)
  493. MSR 0x000000FE = 0x00000000:0x00000D08 (IA32_MTRRCAP)
  494. MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS)
  495. MSR 0x00000175 = 0xFFFFFE00:0x00035200 (IA32_SYSENTER_ESP)
  496. MSR 0x00000176 = 0xFFFFFFFF:0xB3C01790 (IA32_SYSENTER_EIP)
  497. MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP)
  498. MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
  499. MSR 0x00000186 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL0)
  500. MSR 0x00000187 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL1)
  501. MSR 0x00000199 = 0x00000000:0x00001539 (IA32_PERF_CONTROL)
  502. MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION)
  503. MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT)
  504. MSR 0x0000019C = 0x00000000:0x88430000 (IA32_THERM_STATUS)
  505. MSR 0x000001A0 = 0x00000000:0x00850089 (IA32_MISC_ENABLES)
  506. MSR 0x000001B0 = 0x00000000:0x00000006 (IA32_ENERGY_PERF_BIAS)
  507. MSR 0x000001C9 = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS)
  508. MSR 0x000001D9 = 0x00000000:0x00000000 (IA32_DEBUGCTL)
  509. MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LER_FROM_LIP)
  510. MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LER_TO_LIP)
  511. MSR 0x000001F2 = 0x00000000:0xBA000006 (IA32_SMRR_PHYSBASE)
  512. MSR 0x000001F3 = 0x00000000:0xFF800800 (IA32_SMRR_PHYSMASK)
  513. MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0)
  514. MSR 0x00000201 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK0)
  515. MSR 0x00000202 = 0x00000000:0x80000006 (IA32_MTRR_PHYSBASE1)
  516. MSR 0x00000203 = 0x0000000F:0xC0000800 (IA32_MTRR_PHYSMASK1)
  517. MSR 0x00000204 = 0x00000000:0xBA000000 (IA32_MTRR_PHYSBASE2)
  518. MSR 0x00000205 = 0x0000000F:0xFE000800 (IA32_MTRR_PHYSMASK2)
  519. MSR 0x00000206 = 0x00000000:0xBC000000 (IA32_MTRR_PHYSBASE3)
  520. MSR 0x00000207 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK3)
  521. MSR 0x00000208 = 0x00000001:0x00000006 (IA32_MTRR_PHYSBASE4)
  522. MSR 0x00000209 = 0x0000000F:0x00000800 (IA32_MTRR_PHYSMASK4)
  523. MSR 0x0000020A = 0x00000002:0x00000006 (IA32_MTRR_PHYSBASE5)
  524. MSR 0x0000020B = 0x0000000E:0x00000800 (IA32_MTRR_PHYSMASK5)
  525. MSR 0x0000020C = 0x00000004:0x00000006 (IA32_MTRR_PHYSBASE6)
  526. MSR 0x0000020D = 0x0000000F:0xC0000800 (IA32_MTRR_PHYSMASK6)
  527. MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7)
  528. MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7)
  529. MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000)
  530. MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000)
  531. MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000)
  532. MSR 0x00000268 = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_C0000)
  533. MSR 0x00000269 = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_C8000)
  534. MSR 0x0000026A = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_D0000)
  535. MSR 0x0000026B = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_D8000)
  536. MSR 0x0000026C = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E0000)
  537. MSR 0x0000026D = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_E8000)
  538. MSR 0x0000026E = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F0000)
  539. MSR 0x0000026F = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F8000)
  540. MSR 0x00000277 = 0x04070506:0x00070106 (IA32_PAT)
  541. MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE)
  542. MSR 0x00000309 = 0x00000000:0x00000000 (IA32_FIXED_CTR0)
  543. MSR 0x0000030A = 0x000000FD:0xC441E198 (IA32_FIXED_CTR1)
  544. MSR 0x0000030B = 0x00000000:0x00000000 (IA32_FIXED_CTR2)
  545. MSR 0x00000345 = 0x00000000:0x000032C1 (IA32_PERF_CAPABILITIES)
  546. MSR 0x0000038D = 0x00000000:0x000000B0 (IA32_FIXED_CTR_CTRL)
  547. MSR 0x0000038E = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_STATUS)
  548. MSR 0x0000038F = 0x00000007:0x00000003 (IA32_PERF_GLOBAL_CTRL)
  549. MSR 0x00000390 = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_OVF_CTRL)
  550. MSR 0x000003F1 = 0x00000000:0x00000000 (MSR_PEBS_ENABLE)
  551. MSR 0x000003FD = 0x0000010B:0x6CA35840 (MSR_CORE_C6_RESIDENCY)
  552. MSR 0x0000040C = 0x00000000:0x00000003 (IA32_MC3_CTL)
  553. MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS)
  554. MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR)
  555. MSR 0x00000410 = 0x00000000:0x00000001 (IA32_MC4_CTL)
  556. MSR 0x00000411 = 0x00000000:0x00000000 (IA32_MC4_STATUS)
  557. MSR 0x00000412 = 0x00000000:0x00000000 (IA32_MC4_ADDR)
  558. MSR 0x00000480 = 0x00DA0400:0x00000002 (IA32_VMX_BASIC)
  559. MSR 0x00000481 = 0x0000007F:0x00000016 (IA32_VMX_PINBASED_CTLS)
  560. MSR 0x00000482 = 0xFFF9FFFE:0x0401E172 (IA32_VMX_PROCBASED_CTLS)
  561. MSR 0x00000483 = 0x007FFFFF:0x00036DFF (IA32_VMX_EXIT_CTLS)
  562. MSR 0x00000484 = 0x0000FFFF:0x000011FF (IA32_VMX_ENTRY_CTLS)
  563. MSR 0x00000485 = 0x00000000:0x000481E6 (IA32_VMX_MISC)
  564. MSR 0x00000486 = 0x00000000:0x80000021 (IA32_VMX_CR0_FIXED0)
  565. MSR 0x00000487 = 0x00000000:0xFFFFFFFF (IA32_VMX_CR0_FIXED1)
  566. MSR 0x00000488 = 0x00000000:0x00002000 (IA32_VMX_CR4_FIXED0)
  567. MSR 0x00000489 = 0x00000000:0x001027FF (IA32_VMX_CR4_FIXED1)
  568. MSR 0x0000048A = 0x00000000:0x0000002E (IA32_VMX_VMCS_ENUM)
  569. MSR 0x0000048B = 0x000028EF:0x00000000 (IA32_VMX_PROCBASED_CTLS2)
  570. MSR 0x0000048C = 0x00000F01:0x06114141 (IA32_VMX_EPT_VPID_ENUM)
  571. MSR 0x0000048D = 0x0000007F:0x00000016 (IA32_VMX_TRUE_PINBASED_CTLS)
  572. MSR 0x0000048E = 0xFFF9FFFE:0x04006172 (IA32_VMX_TRUE_PROCBASED_CTLS)
  573. MSR 0x0000048F = 0x007FFFFF:0x00036DFB (IA32_VMX_TRUE_EXIT_CTLS)
  574. MSR 0x00000490 = 0x0000FFFF:0x000011FB (IA32_VMX_TRUE_ENTRY_CTLS)
  575. MSR 0x00000491 = 0x00000000:0x00000001 (IA32_VMX_FMFUNC)
  576. MSR 0x000004C1 = 0x00000000:0x00000000 (IA32_A_PMC0)
  577. MSR 0x000004C2 = 0x00000000:0x00000000 (IA32_A_PMC1)
  578. MSR 0x00000600 = 0xFFFFFE00:0x00046000 (IA32_DS_AREA)
  579. MSR 0x00000660 = 0x00000002:0xC40BBCC8 (MSR_CORE_C1_RESIDENCY)
  580. MSR 0x000006E0 = 0x000001B0:0x2B25FD18 (IA32_TSC_DEADLINE)
  581.  
  582. ====================== UNIQUE MSRs (core 2) ======================
  583. MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE)
  584. MSR 0x00000010 = 0x000001B0:0x2B17E658 (IA32_TIME_STAMP_COUNTER)
  585. MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE)
  586. MSR 0x00000034 = 0x00000000:0x00004CDC (MSR_SMI_COUNT)
  587. MSR 0x0000003A = 0x00000000:0x00000005 (IA32_FEATURE_CONTROL)
  588. MSR 0x00000040 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_FROM_IP)
  589. MSR 0x00000041 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_FROM_IP)
  590. MSR 0x00000042 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_FROM_IP)
  591. MSR 0x00000043 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_FROM_IP)
  592. MSR 0x00000044 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_FROM_IP)
  593. MSR 0x00000045 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_FROM_IP)
  594. MSR 0x00000046 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_FROM_IP)
  595. MSR 0x00000047 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_FROM_IP)
  596. MSR 0x00000060 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_TO_IP)
  597. MSR 0x00000061 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_TO_IP)
  598. MSR 0x00000062 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_TO_IP)
  599. MSR 0x00000063 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_TO_IP)
  600. MSR 0x00000064 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_TO_IP)
  601. MSR 0x00000065 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_TO_IP)
  602. MSR 0x00000066 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_TO_IP)
  603. MSR 0x00000067 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_TO_IP)
  604. MSR 0x0000008B = 0x00000838:0x00000000 (IA32_BIOS_SIGN_ID)
  605. MSR 0x000000C1 = 0x00000000:0x00000000 (IA32_PMC0)
  606. MSR 0x000000C2 = 0x00000000:0x00000000 (IA32_PMC1)
  607. MSR 0x000000E7 = 0x00000019:0xB30AE5A0 (IA32_MPERF)
  608. MSR 0x000000E8 = 0x0000001C:0x176ADEA0 (IA32_APERF)
  609. MSR 0x000000FE = 0x00000000:0x00000D08 (IA32_MTRRCAP)
  610. MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS)
  611. MSR 0x00000175 = 0xFFFFFE00:0x00068200 (IA32_SYSENTER_ESP)
  612. MSR 0x00000176 = 0xFFFFFFFF:0xB3C01790 (IA32_SYSENTER_EIP)
  613. MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP)
  614. MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
  615. MSR 0x00000186 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL0)
  616. MSR 0x00000187 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL1)
  617. MSR 0x00000199 = 0x00000000:0x0000102F (IA32_PERF_CONTROL)
  618. MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION)
  619. MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT)
  620. MSR 0x0000019C = 0x00000000:0x88420000 (IA32_THERM_STATUS)
  621. MSR 0x000001A0 = 0x00000000:0x00850089 (IA32_MISC_ENABLES)
  622. MSR 0x000001B0 = 0x00000000:0x00000006 (IA32_ENERGY_PERF_BIAS)
  623. MSR 0x000001C9 = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS)
  624. MSR 0x000001D9 = 0x00000000:0x00000000 (IA32_DEBUGCTL)
  625. MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LER_FROM_LIP)
  626. MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LER_TO_LIP)
  627. MSR 0x000001F2 = 0x00000000:0xBA000006 (IA32_SMRR_PHYSBASE)
  628. MSR 0x000001F3 = 0x00000000:0xFF800800 (IA32_SMRR_PHYSMASK)
  629. MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0)
  630. MSR 0x00000201 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK0)
  631. MSR 0x00000202 = 0x00000000:0x80000006 (IA32_MTRR_PHYSBASE1)
  632. MSR 0x00000203 = 0x0000000F:0xC0000800 (IA32_MTRR_PHYSMASK1)
  633. MSR 0x00000204 = 0x00000000:0xBA000000 (IA32_MTRR_PHYSBASE2)
  634. MSR 0x00000205 = 0x0000000F:0xFE000800 (IA32_MTRR_PHYSMASK2)
  635. MSR 0x00000206 = 0x00000000:0xBC000000 (IA32_MTRR_PHYSBASE3)
  636. MSR 0x00000207 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK3)
  637. MSR 0x00000208 = 0x00000001:0x00000006 (IA32_MTRR_PHYSBASE4)
  638. MSR 0x00000209 = 0x0000000F:0x00000800 (IA32_MTRR_PHYSMASK4)
  639. MSR 0x0000020A = 0x00000002:0x00000006 (IA32_MTRR_PHYSBASE5)
  640. MSR 0x0000020B = 0x0000000E:0x00000800 (IA32_MTRR_PHYSMASK5)
  641. MSR 0x0000020C = 0x00000004:0x00000006 (IA32_MTRR_PHYSBASE6)
  642. MSR 0x0000020D = 0x0000000F:0xC0000800 (IA32_MTRR_PHYSMASK6)
  643. MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7)
  644. MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7)
  645. MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000)
  646. MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000)
  647. MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000)
  648. MSR 0x00000268 = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_C0000)
  649. MSR 0x00000269 = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_C8000)
  650. MSR 0x0000026A = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_D0000)
  651. MSR 0x0000026B = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_D8000)
  652. MSR 0x0000026C = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E0000)
  653. MSR 0x0000026D = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_E8000)
  654. MSR 0x0000026E = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F0000)
  655. MSR 0x0000026F = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F8000)
  656. MSR 0x00000277 = 0x04070506:0x00070106 (IA32_PAT)
  657. MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE)
  658. MSR 0x00000309 = 0x00000000:0x00000000 (IA32_FIXED_CTR0)
  659. MSR 0x0000030A = 0x000000FD:0x07899516 (IA32_FIXED_CTR1)
  660. MSR 0x0000030B = 0x00000000:0x00000000 (IA32_FIXED_CTR2)
  661. MSR 0x00000345 = 0x00000000:0x000032C1 (IA32_PERF_CAPABILITIES)
  662. MSR 0x0000038D = 0x00000000:0x000000B0 (IA32_FIXED_CTR_CTRL)
  663. MSR 0x0000038E = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_STATUS)
  664. MSR 0x0000038F = 0x00000007:0x00000003 (IA32_PERF_GLOBAL_CTRL)
  665. MSR 0x00000390 = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_OVF_CTRL)
  666. MSR 0x000003F1 = 0x00000000:0x00000000 (MSR_PEBS_ENABLE)
  667. MSR 0x000003FD = 0x00000109:0x9161CC90 (MSR_CORE_C6_RESIDENCY)
  668. MSR 0x0000040C = 0x00000000:0x00000003 (IA32_MC3_CTL)
  669. MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS)
  670. MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR)
  671. MSR 0x00000410 = 0x00000000:0x00000001 (IA32_MC4_CTL)
  672. MSR 0x00000411 = 0x00000000:0x00000000 (IA32_MC4_STATUS)
  673. MSR 0x00000412 = 0x00000000:0x00000000 (IA32_MC4_ADDR)
  674. MSR 0x00000480 = 0x00DA0400:0x00000002 (IA32_VMX_BASIC)
  675. MSR 0x00000481 = 0x0000007F:0x00000016 (IA32_VMX_PINBASED_CTLS)
  676. MSR 0x00000482 = 0xFFF9FFFE:0x0401E172 (IA32_VMX_PROCBASED_CTLS)
  677. MSR 0x00000483 = 0x007FFFFF:0x00036DFF (IA32_VMX_EXIT_CTLS)
  678. MSR 0x00000484 = 0x0000FFFF:0x000011FF (IA32_VMX_ENTRY_CTLS)
  679. MSR 0x00000485 = 0x00000000:0x000481E6 (IA32_VMX_MISC)
  680. MSR 0x00000486 = 0x00000000:0x80000021 (IA32_VMX_CR0_FIXED0)
  681. MSR 0x00000487 = 0x00000000:0xFFFFFFFF (IA32_VMX_CR0_FIXED1)
  682. MSR 0x00000488 = 0x00000000:0x00002000 (IA32_VMX_CR4_FIXED0)
  683. MSR 0x00000489 = 0x00000000:0x001027FF (IA32_VMX_CR4_FIXED1)
  684. MSR 0x0000048A = 0x00000000:0x0000002E (IA32_VMX_VMCS_ENUM)
  685. MSR 0x0000048B = 0x000028EF:0x00000000 (IA32_VMX_PROCBASED_CTLS2)
  686. MSR 0x0000048C = 0x00000F01:0x06114141 (IA32_VMX_EPT_VPID_ENUM)
  687. MSR 0x0000048D = 0x0000007F:0x00000016 (IA32_VMX_TRUE_PINBASED_CTLS)
  688. MSR 0x0000048E = 0xFFF9FFFE:0x04006172 (IA32_VMX_TRUE_PROCBASED_CTLS)
  689. MSR 0x0000048F = 0x007FFFFF:0x00036DFB (IA32_VMX_TRUE_EXIT_CTLS)
  690. MSR 0x00000490 = 0x0000FFFF:0x000011FB (IA32_VMX_TRUE_ENTRY_CTLS)
  691. MSR 0x00000491 = 0x00000000:0x00000001 (IA32_VMX_FMFUNC)
  692. MSR 0x000004C1 = 0x00000000:0x00000000 (IA32_A_PMC0)
  693. MSR 0x000004C2 = 0x00000000:0x00000000 (IA32_A_PMC1)
  694. MSR 0x00000600 = 0xFFFFFE00:0x00079000 (IA32_DS_AREA)
  695. MSR 0x00000660 = 0x00000002:0x9E53B808 (MSR_CORE_C1_RESIDENCY)
  696. MSR 0x000006E0 = 0x000001B0:0x2BF15B80 (IA32_TSC_DEADLINE)
  697.  
  698. ====================== UNIQUE MSRs (core 3) ======================
  699. MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE)
  700. MSR 0x00000010 = 0x000001B0:0x2BC8AA10 (IA32_TIME_STAMP_COUNTER)
  701. MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE)
  702. MSR 0x00000034 = 0x00000000:0x00004CDC (MSR_SMI_COUNT)
  703. MSR 0x0000003A = 0x00000000:0x00000005 (IA32_FEATURE_CONTROL)
  704. MSR 0x00000040 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_FROM_IP)
  705. MSR 0x00000041 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_FROM_IP)
  706. MSR 0x00000042 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_FROM_IP)
  707. MSR 0x00000043 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_FROM_IP)
  708. MSR 0x00000044 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_FROM_IP)
  709. MSR 0x00000045 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_FROM_IP)
  710. MSR 0x00000046 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_FROM_IP)
  711. MSR 0x00000047 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_FROM_IP)
  712. MSR 0x00000060 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_TO_IP)
  713. MSR 0x00000061 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_TO_IP)
  714. MSR 0x00000062 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_TO_IP)
  715. MSR 0x00000063 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_TO_IP)
  716. MSR 0x00000064 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_TO_IP)
  717. MSR 0x00000065 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_TO_IP)
  718. MSR 0x00000066 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_TO_IP)
  719. MSR 0x00000067 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_TO_IP)
  720. MSR 0x0000008B = 0x00000838:0x00000000 (IA32_BIOS_SIGN_ID)
  721. MSR 0x000000C1 = 0x00000000:0x00000000 (IA32_PMC0)
  722. MSR 0x000000C2 = 0x00000000:0x00000000 (IA32_PMC1)
  723. MSR 0x000000E7 = 0x00000012:0x0B9092E0 (IA32_MPERF)
  724. MSR 0x000000E8 = 0x00000013:0x8258E3EC (IA32_APERF)
  725. MSR 0x000000FE = 0x00000000:0x00000D08 (IA32_MTRRCAP)
  726. MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS)
  727. MSR 0x00000175 = 0xFFFFFE00:0x0009B200 (IA32_SYSENTER_ESP)
  728. MSR 0x00000176 = 0xFFFFFFFF:0xB3C01790 (IA32_SYSENTER_EIP)
  729. MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP)
  730. MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
  731. MSR 0x00000186 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL0)
  732. MSR 0x00000187 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL1)
  733. MSR 0x00000199 = 0x00000000:0x0000102F (IA32_PERF_CONTROL)
  734. MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION)
  735. MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT)
  736. MSR 0x0000019C = 0x00000000:0x88420000 (IA32_THERM_STATUS)
  737. MSR 0x000001A0 = 0x00000000:0x00850089 (IA32_MISC_ENABLES)
  738. MSR 0x000001B0 = 0x00000000:0x00000006 (IA32_ENERGY_PERF_BIAS)
  739. MSR 0x000001C9 = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS)
  740. MSR 0x000001D9 = 0x00000000:0x00000000 (IA32_DEBUGCTL)
  741. MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LER_FROM_LIP)
  742. MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LER_TO_LIP)
  743. MSR 0x000001F2 = 0x00000000:0xBA000006 (IA32_SMRR_PHYSBASE)
  744. MSR 0x000001F3 = 0x00000000:0xFF800800 (IA32_SMRR_PHYSMASK)
  745. MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0)
  746. MSR 0x00000201 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK0)
  747. MSR 0x00000202 = 0x00000000:0x80000006 (IA32_MTRR_PHYSBASE1)
  748. MSR 0x00000203 = 0x0000000F:0xC0000800 (IA32_MTRR_PHYSMASK1)
  749. MSR 0x00000204 = 0x00000000:0xBA000000 (IA32_MTRR_PHYSBASE2)
  750. MSR 0x00000205 = 0x0000000F:0xFE000800 (IA32_MTRR_PHYSMASK2)
  751. MSR 0x00000206 = 0x00000000:0xBC000000 (IA32_MTRR_PHYSBASE3)
  752. MSR 0x00000207 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK3)
  753. MSR 0x00000208 = 0x00000001:0x00000006 (IA32_MTRR_PHYSBASE4)
  754. MSR 0x00000209 = 0x0000000F:0x00000800 (IA32_MTRR_PHYSMASK4)
  755. MSR 0x0000020A = 0x00000002:0x00000006 (IA32_MTRR_PHYSBASE5)
  756. MSR 0x0000020B = 0x0000000E:0x00000800 (IA32_MTRR_PHYSMASK5)
  757. MSR 0x0000020C = 0x00000004:0x00000006 (IA32_MTRR_PHYSBASE6)
  758. MSR 0x0000020D = 0x0000000F:0xC0000800 (IA32_MTRR_PHYSMASK6)
  759. MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7)
  760. MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7)
  761. MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000)
  762. MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000)
  763. MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000)
  764. MSR 0x00000268 = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_C0000)
  765. MSR 0x00000269 = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_C8000)
  766. MSR 0x0000026A = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_D0000)
  767. MSR 0x0000026B = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_D8000)
  768. MSR 0x0000026C = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E0000)
  769. MSR 0x0000026D = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_E8000)
  770. MSR 0x0000026E = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F0000)
  771. MSR 0x0000026F = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F8000)
  772. MSR 0x00000277 = 0x04070506:0x00070106 (IA32_PAT)
  773. MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE)
  774. MSR 0x00000309 = 0x00000000:0x00000000 (IA32_FIXED_CTR0)
  775. MSR 0x0000030A = 0x000000FD:0xAB2409B5 (IA32_FIXED_CTR1)
  776. MSR 0x0000030B = 0x00000000:0x00000000 (IA32_FIXED_CTR2)
  777. MSR 0x00000345 = 0x00000000:0x000032C1 (IA32_PERF_CAPABILITIES)
  778. MSR 0x0000038D = 0x00000000:0x000000B0 (IA32_FIXED_CTR_CTRL)
  779. MSR 0x0000038E = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_STATUS)
  780. MSR 0x0000038F = 0x00000007:0x00000003 (IA32_PERF_GLOBAL_CTRL)
  781. MSR 0x00000390 = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_OVF_CTRL)
  782. MSR 0x000003F1 = 0x00000000:0x00000000 (MSR_PEBS_ENABLE)
  783. MSR 0x000003FD = 0x00000110:0x65405260 (MSR_CORE_C6_RESIDENCY)
  784. MSR 0x0000040C = 0x00000000:0x00000003 (IA32_MC3_CTL)
  785. MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS)
  786. MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR)
  787. MSR 0x00000410 = 0x00000000:0x00000001 (IA32_MC4_CTL)
  788. MSR 0x00000411 = 0x00000000:0x00000000 (IA32_MC4_STATUS)
  789. MSR 0x00000412 = 0x00000000:0x00000000 (IA32_MC4_ADDR)
  790. MSR 0x00000480 = 0x00DA0400:0x00000002 (IA32_VMX_BASIC)
  791. MSR 0x00000481 = 0x0000007F:0x00000016 (IA32_VMX_PINBASED_CTLS)
  792. MSR 0x00000482 = 0xFFF9FFFE:0x0401E172 (IA32_VMX_PROCBASED_CTLS)
  793. MSR 0x00000483 = 0x007FFFFF:0x00036DFF (IA32_VMX_EXIT_CTLS)
  794. MSR 0x00000484 = 0x0000FFFF:0x000011FF (IA32_VMX_ENTRY_CTLS)
  795. MSR 0x00000485 = 0x00000000:0x000481E6 (IA32_VMX_MISC)
  796. MSR 0x00000486 = 0x00000000:0x80000021 (IA32_VMX_CR0_FIXED0)
  797. MSR 0x00000487 = 0x00000000:0xFFFFFFFF (IA32_VMX_CR0_FIXED1)
  798. MSR 0x00000488 = 0x00000000:0x00002000 (IA32_VMX_CR4_FIXED0)
  799. MSR 0x00000489 = 0x00000000:0x001027FF (IA32_VMX_CR4_FIXED1)
  800. MSR 0x0000048A = 0x00000000:0x0000002E (IA32_VMX_VMCS_ENUM)
  801. MSR 0x0000048B = 0x000028EF:0x00000000 (IA32_VMX_PROCBASED_CTLS2)
  802. MSR 0x0000048C = 0x00000F01:0x06114141 (IA32_VMX_EPT_VPID_ENUM)
  803. MSR 0x0000048D = 0x0000007F:0x00000016 (IA32_VMX_TRUE_PINBASED_CTLS)
  804. MSR 0x0000048E = 0xFFF9FFFE:0x04006172 (IA32_VMX_TRUE_PROCBASED_CTLS)
  805. MSR 0x0000048F = 0x007FFFFF:0x00036DFB (IA32_VMX_TRUE_EXIT_CTLS)
  806. MSR 0x00000490 = 0x0000FFFF:0x000011FB (IA32_VMX_TRUE_ENTRY_CTLS)
  807. MSR 0x00000491 = 0x00000000:0x00000001 (IA32_VMX_FMFUNC)
  808. MSR 0x000004C1 = 0x00000000:0x00000000 (IA32_A_PMC0)
  809. MSR 0x000004C2 = 0x00000000:0x00000000 (IA32_A_PMC1)
  810. MSR 0x00000600 = 0xFFFFFE00:0x000AC000 (IA32_DS_AREA)
  811. MSR 0x00000660 = 0x00000003:0xDAADB600 (MSR_CORE_C1_RESIDENCY)
  812. MSR 0x000006E0 = 0x000001B0:0xC14753F0 (IA32_TSC_DEADLINE)
  813.  
  814.  
  815.  
  816. ============= AMBs ============
  817.  
  818.  
  819. ============= SPI / BIOS CNTL =============
  820.  
  821. Error: Dumping SPI on this southbridge is not (yet) supported.
  822. No SATA device found
  823.  
  824. ============= Dumping INTEL SGX status =============
  825. Number of CPUs = 4
  826. ------------- CPU 0 ----------------
  827. SGX supported : NO
  828. SGX enabled : NO
  829. Feature Control locked : YES
  830. ------------- CPU 1 ----------------
  831. SGX supported : NO
  832. SGX enabled : NO
  833. Feature Control locked : YES
  834. ------------- CPU 2 ----------------
  835. SGX supported : NO
  836. SGX enabled : NO
  837. Feature Control locked : YES
  838. ------------- CPU 3 ----------------
  839. SGX supported : NO
  840. SGX enabled : NO
  841. Feature Control locked : YES
  842. ====================================================
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