library ieee;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity priprema2_tb is
end priprema2_tb;
architecture Test_tb of priprema2_tb is
	signal sLOAD : std_logic;
	signal sCLK: std_logic;
	signal sRST : std_logic;
	signal sD : std_logic_vector(7 downto 0);
	signal sONES: std_logic_vector(7 downto 0);
	signal sEVEN: std_logic_vector(2 downto 0);
	signal sODD: std_logic_vector(2 downto 0);
component priprema2
port(
	iLOAD : in std_logic;
	iCLK: in std_logic;
	iRST : in std_logic;
	iD : in std_logic_vector(7 downto 0);
	oONES: out std_logic_vector(7 downto 0);
	oEVEN: out std_logic_vector(2 downto 0);
	oODD: out std_logic_vector(2 downto 0)
 );
end component;

constant iCLK_period : time := 10 ns;


begin
uut: priprema2 port map (
	iLOAD	=> sLOAD,
   iCLK	=> sCLK,
   iRST	=> sRST,
   iD  	=> sD,
   oONES	=> sONES,
   oEVEN	=> sEVEN,
   oODD	=> sODD

);

iCLK_process: process
begin
	sCLK <= '0';
	wait for iCLK_period / 2;
	sCLK <= '1';
	wait for iCLK_period / 2;
end process;


process
begin
	sRST <= '0';
	wait for 5.25 * iCLK_period;
	sRST <= '1';

	sD <= "00101010";
	sLOAD <= '1';
	wait for iCLK_period;
	sLOAD <= '0';
	wait for 8 * iCLK_period;
	sD <= "00100011";
	sLOAD <= '1';
	wait for iCLK_period;
	sLOAD <= '0';
	wait for 8 * iCLK_period;
	sD <= "00010011";
	sLOAD <= '1';
	wait for iCLK_period;
	sLOAD <= '0';
	wait for 8 * iCLK_period;
	sD <= "10000010";
	sLOAD <= '1';
	wait for iCLK_period;
	sLOAD <= '0';
	wait for 8 * iCLK_period;
	sD <= "00110011";
	sLOAD <= '1';
	wait for iCLK_period;
	sLOAD <= '0';



	wait;

end process;

end architecture;