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- /************************************************************************
- Avalon-MM Interface for AES Decryption IP Core
- Dong Kai Wang, Fall 2017
- For use with ECE 385 Experiment 9
- University of Illinois ECE Department
- Register Map:
- 0-3 : 4x 32bit AES Key
- 4-7 : 4x 32bit AES Encrypted Message
- 8-11: 4x 32bit AES Decrypted Message
- 12: Not Used
- 13: Not Used
- 14: 32bit Start Register
- 15: 32bit Done Register
- ************************************************************************/
- module avalon_aes_interface (
- // Avalon Clock Input
- input logic CLK,
- // Avalon Reset Input
- input logic RESET,
- // Avalon-MM Slave Signals
- input logic AVL_READ, // Avalon-MM Read
- input logic AVL_WRITE, // Avalon-MM Write
- input logic AVL_CS, // Avalon-MM Chip Select
- input logic [3:0] AVL_BYTE_EN, // Avalon-MM Byte Enable
- input logic [3:0] AVL_ADDR, // Avalon-MM Address
- input logic [31:0] AVL_WRITEDATA, // Avalon-MM Write Data
- output logic [31:0] AVL_READDATA, // Avalon-MM Read Data
- // Exported Conduit
- output logic [31:0] EXPORT_DATA // Exported Conduit Signal to LEDs
- );
- // an unpacked array of 32-bit registers
- logic [31:0] reggy [15:0];
- // Assign variables for the AES interface variables
- logic [127:0] AES_MSG_DEC;
- logic AES_DONE;
- logic AES_START;
- logic [127:0] AES_KEY;
- logic [127:0] AES_MSG_ENC;
- assign AES_MSG_ENC = {reggy[4], reggy[5], reggy[6], reggy[7]};
- assign AES_START = reggy[14][0];
- assign AES_KEY = {reggy[0], reggy[1], reggy[2], reggy[3]};
- // Instantiate AES interface to get AES_MSG_DEC
- AES aes(.*);
- always_ff @ (posedge CLK)
- begin
- // Reset is active HIGH
- if(RESET)
- begin
- // initialize register contents to 0
- reggy[0] <= 32'b0;
- reggy[1] <= 32'b0;
- reggy[2] <= 32'b0;
- reggy[3] <= 32'b0;
- reggy[4] <= 32'b0;
- reggy[5] <= 32'b0;
- reggy[6] <= 32'b0;
- reggy[7] <= 32'b0;
- reggy[8] <= 32'b0;
- reggy[9] <= 32'b0;
- reggy[10] <= 32'b0;
- reggy[11] <= 32'b0;
- reggy[12] <= 32'b0;
- reggy[13] <= 32'b0;
- reggy[14] <= 32'b0;
- end
- else if(AVL_CS)
- begin
- if(AVL_WRITE)
- begin
- // depending on which register is the destination register, load contents from data bus into
- // that register
- case(AVL_ADDR)
- 4'b0000:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[0][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[0][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[0][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[0][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[0][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[0][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[0] <= AVL_WRITEDATA;
- endcase
- end
- 4'b0001:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[1][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[1][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[1][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[1][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[1][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[1][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[1] <= AVL_WRITEDATA;
- endcase
- end
- 4'b0010:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[2][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[2][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[2][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[2][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[2][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[2][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[2] <= AVL_WRITEDATA;
- endcase
- end
- 4'b0011:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[3][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[3][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[3][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[3][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[3][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[3][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[3] <= AVL_WRITEDATA;
- endcase
- end
- 4'b0100:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[4][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[4][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[4][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[4][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[4][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[4][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[4] <= AVL_WRITEDATA;
- endcase
- end
- 4'b0101:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[5][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[5][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[5][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[5][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[5][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[5][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[5] <= AVL_WRITEDATA;
- endcase
- end
- 4'b0110:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[6][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[6][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[6][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[6][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[6][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[6][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[6] <= AVL_WRITEDATA;
- endcase
- end
- 4'b0111:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[7][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[7][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[7][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[7][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[7][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[7][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[7] <= AVL_WRITEDATA;
- endcase
- end
- 4'b1000:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[8][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[8][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[8][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[8][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[8][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[8][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[8] <= AVL_WRITEDATA;
- endcase
- end
- 4'b1001:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[9][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[9][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[9][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[9][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[9][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[9][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[9] <= AVL_WRITEDATA;
- endcase
- end
- 4'b1010:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[10][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[10][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[10][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[10][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[10][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[10][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[10] <= AVL_WRITEDATA;
- endcase
- end
- 4'b1011:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[11][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[11][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[11][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[11][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[11][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[11][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[11] <= AVL_WRITEDATA;
- endcase
- end
- 4'b1100:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[12][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[12][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[12][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[12][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[12][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[12][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[12] <= AVL_WRITEDATA;
- endcase
- end
- 4'b1101:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[13][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[13][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[13][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[13][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[13][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[13][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[13] <= AVL_WRITEDATA;
- endcase
- end
- 4'b1110:
- begin
- case(AVL_BYTE_EN)
- 4'b0001 : reggy[14][7:0] <= AVL_WRITEDATA;
- 4'b0010 : reggy[14][15:8] <= AVL_WRITEDATA;
- 4'b0100 : reggy[14][23:16] <= AVL_WRITEDATA;
- 4'b1000 : reggy[14][31:24] <= AVL_WRITEDATA;
- 4'b0011 : reggy[14][15:0] <= AVL_WRITEDATA;
- 4'b1100 : reggy[14][31:16] <= AVL_WRITEDATA;
- 4'b1111 : reggy[14] <= AVL_WRITEDATA;
- endcase
- end
- 4'b1111: ;
- default: ;
- endcase
- end
- else if(AES_DONE)
- begin
- reggy[11] <= AES_MSG_DEC[127:96];
- reggy[10] <= AES_MSG_DEC[95:64];
- reggy[9] <= AES_MSG_DEC[63:32];
- reggy[8] <= AES_MSG_DEC[31:0];
- end
- else
- begin
- reggy[0] <= reggy[0];
- reggy[1] <= reggy[1];
- reggy[2] <= reggy[2];
- reggy[3] <= reggy[3];
- reggy[4] <= reggy[4];
- reggy[5] <= reggy[5];
- reggy[6] <= reggy[6];
- reggy[7] <= reggy[7];
- reggy[8] <= reggy[8];
- reggy[9] <= reggy[9];
- reggy[10] <= reggy[10];
- reggy[11] <= reggy[11];
- reggy[12] <= reggy[12];
- reggy[13] <= reggy[13];
- reggy[14] <= reggy[14];
- end
- end
- end
- always_comb
- begin
- if(AVL_READ && AVL_CS)
- AVL_READDATA = reggy[AVL_ADDR];
- else
- AVL_READDATA = 32'bx;
- end
- assign EXPORT_DATA = {reggy[4][31:16] , reggy[7][15:0]};
- assign reggy[15] = {31'b0, AES_DONE};
- endmodule
- //
- //
- ///************************************************************************
- //Avalon-MM Interface for AES Decryption IP Core
- //
- //Dong Kai Wang, Fall 2017
- //
- //For use with ECE 385 Experiment 9
- //University of Illinois ECE Department
- //
- //Register Map:
- //
- // 0-3 : 4x 32bit AES Key
- // 4-7 : 4x 32bit AES Encrypted Message
- // 8-11: 4x 32bit AES Decrypted Message
- // 12: Not Used
- // 13: Not Used
- // 14: 32bit Start Register
- // 15: 32bit Done Register
- //
- //************************************************************************/
- //
- //module avalon_aes_interface (
- // // Avalon Clock Input
- // input logic CLK,
- //
- // // Avalon Reset Input
- // input logic RESET,
- //
- // // Avalon-MM Slave Signals
- // input logic AVL_READ, // Avalon-MM Read
- // input logic AVL_WRITE, // Avalon-MM Write
- // input logic AVL_CS, // Avalon-MM Chip Select
- // input logic [3:0] AVL_BYTE_EN, // Avalon-MM Byte Enable
- // input logic [3:0] AVL_ADDR, // Avalon-MM Address
- // input logic [31:0] AVL_WRITEDATA, // Avalon-MM Write Data
- // output logic [31:0] AVL_READDATA, // Avalon-MM Read Data
- //
- // // Exported Conduit
- // output logic [31:0] EXPORT_DATA // Exported Conduit Signal to LEDs
- //);
- //
- // logic [15:0][31:0] output_arr;
- // logic [127:0] decoded_msg;
- // logic done;
- //// logic [127:0] lastditch_out;
- //
- //// assign EXPORT_DATA = {output_arr[4][31:16], output_arr[7][15:0]}; encrypted message
- //// assign EXPORT_DATA = {output_arr[0][31:16], output_arr[3][15:0]}; key
- // assign EXPORT_DATA = {output_arr[11][31:16], output_arr[8][15:0]};
- //
- // //BEGIN REGISTER FILE
- // always_ff @ (posedge CLK) begin
- // if (RESET) begin
- // output_arr[0] <= 32'h0;
- // output_arr[1] <= 32'h0;
- // output_arr[2] <= 32'h0;
- // output_arr[3] <= 32'h0;
- // output_arr[4] <= 32'h0;
- // output_arr[5] <= 32'h0;
- // output_arr[6] <= 32'h0;
- // output_arr[7] <= 32'h0;
- // output_arr[8] <= 32'h0;
- // output_arr[9] <= 32'h0;
- // output_arr[10] <= 32'h0;
- // output_arr[11] <= 32'h0;
- //// output_arr[8] <= decoded_msg[31:0];
- //// output_arr[9] <= decoded_msg[63:32];
- //// output_arr[10] <= decoded_msg[95:64];
- //// output_arr[11] <= decoded_msg[127:96];
- // output_arr[12] <= 32'h0;
- // output_arr[13] <= 32'h0;
- // output_arr[14] <= 32'h0;
- // output_arr[15] <= 32'h0;
- // end
- // else if (done == 1'b1)
- // begin
- // output_arr[8] <= decoded_msg[127:96];
- // output_arr[9] <= decoded_msg[95:64];
- // output_arr[10] <= decoded_msg[63:32];
- // output_arr[11] <= decoded_msg[31:0];
- //// output_arr[15] <= 32'h00000001;
- //// output_arr[8] <= 32'hEEADBEEF;
- //// output_arr[9] <= 32'hBEADFAAF;
- //// output_arr[10] <= 32'hCEEDFEED;
- //// output_arr[11] <= 32'hDEADBEEB;
- // end
- // else if (AVL_WRITE & AVL_CS)
- // case(AVL_ADDR)
- // 4'd0:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[0][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[0][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[0][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[0][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[0][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[0][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[0] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // 4'd1:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[1][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[1][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[1][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[1][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[1][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[1][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[1] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // 4'd2:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[2][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[2][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[2][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[2][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[2][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[2][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[2] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // 4'd3:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[3][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[3][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[3][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[3][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[3][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[3][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[3] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // 4'd4:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[4][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[4][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[4][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[4][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[4][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[4][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[4] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // 4'd5:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[5][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[5][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[5][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[5][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[5][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[5][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[5] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // 4'd6:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[6][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[6][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[6][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[6][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[6][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[6][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[6] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // 4'd7:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[7][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[7][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[7][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[7][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[7][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[7][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[7] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- ////
- //// 4'd8:
- //// output_arr[8] <= lastditch_out[31:0];
- ////
- //// 4'd9:
- //// output_arr[9] <= lastditch_out[63:32];
- ////
- //// 4'd10:
- //// output_arr[10] <= lastditch_out[95:64];
- ////
- //// 4'd11:
- //// output_arr[11] <= lastditch_out[127:97];
- //
- // 4'd12:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[12][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[12][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[12][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[12][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[12][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[12][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[12] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // 4'd13:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[13][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[13][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[13][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[13][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[13][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[13][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[13] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // 4'd14:
- // case(AVL_BYTE_EN)
- // 4'b0001:
- // output_arr[14][7:0] <= AVL_WRITEDATA[7:0];
- // 4'b0010:
- // output_arr[14][15:8] <= AVL_WRITEDATA[15:8];
- // 4'b0100:
- // output_arr[14][23:16] <= AVL_WRITEDATA[23:16];
- // 4'b1000:
- // output_arr[14][31:24] <= AVL_WRITEDATA[31:24];
- // 4'b0011:
- // begin
- // output_arr[14][15:0] <= AVL_WRITEDATA[15:0];
- // end
- // 4'b1100:
- // begin
- // output_arr[14][31:16] <= AVL_WRITEDATA[31:16];
- // end
- // 4'b1111:
- // output_arr[14] <= AVL_WRITEDATA;
- // default: ;
- // endcase
- //
- // // nothin for 15 lolol
- //
- // default: ;
- // endcase
- // else begin
- // output_arr[0] <= output_arr[0];
- // output_arr[1] <= output_arr[1];
- // output_arr[2] <= output_arr[2];
- // output_arr[3] <= output_arr[3];
- // output_arr[4] <= output_arr[4];
- // output_arr[5] <= output_arr[5];
- // output_arr[6] <= output_arr[6];
- // output_arr[7] <= output_arr[7];
- // output_arr[8] <= output_arr[8];
- // output_arr[9] <= output_arr[9];
- // output_arr[10] <= output_arr[10];
- // output_arr[11] <= output_arr[11];
- // output_arr[12] <= output_arr[12];
- // output_arr[13] <= output_arr[13];
- // output_arr[14] <= output_arr[14];
- //// output_arr[15] <= output_arr[15];
- // end
- //
- // output_arr[15] <= {31'b0, done};
- // end
- //
- // always_comb begin
- // if (AVL_READ & AVL_CS) begin
- // case(AVL_ADDR)
- // 4'd0:
- // AVL_READDATA = output_arr[0];
- // 4'd1:
- // AVL_READDATA = output_arr[1];
- // 4'd2:
- // AVL_READDATA = output_arr[2];
- // 4'd3:
- // AVL_READDATA = output_arr[3];
- // 4'd4:
- // AVL_READDATA = output_arr[4];
- // 4'd5:
- // AVL_READDATA = output_arr[5];
- // 4'd6:
- // AVL_READDATA = output_arr[6];
- // 4'd7:
- // AVL_READDATA = output_arr[7];
- // 4'd8:
- // AVL_READDATA = output_arr[8];
- // 4'd9:
- // AVL_READDATA = output_arr[9];
- // 4'd10:
- // AVL_READDATA = output_arr[10];
- // 4'd11:
- // AVL_READDATA = output_arr[11];
- // 4'd12:
- // AVL_READDATA = output_arr[12];
- // 4'd13:
- // AVL_READDATA = output_arr[13];
- // 4'd14:
- // AVL_READDATA = output_arr[14];
- // 4'd15:
- // AVL_READDATA = output_arr[15];
- // default: ;
- // endcase
- // end
- //
- // else begin
- // AVL_READDATA = 32'bX;
- // end
- // end
- // //END REGISTER FILE
- //
- // //Decryption
- // AES decryptboi(
- // .CLK,
- // .RESET,
- // .AES_START(output_arr[14][0]),
- // .AES_DONE(done),
- //// .AES_KEY(output_arr[3:0]),
- // .AES_KEY({output_arr[0], output_arr[1], output_arr[2], output_arr[3]}),
- //// .AES_MSG_ENC(output_arr[7:4]),
- // .AES_MSG_ENC({output_arr[4], output_arr[5], output_arr[6], output_arr[7]}),
- // .AES_MSG_DEC(decoded_msg)
- // );
- //
- //// reg_128_ld lastditch(.Clk(CLK), .Reset(RESET), .Load(done), .D(decoded_msg), .Dout(lastditch_out));
- //
- //endmodule
- //
- ////module reg_128_ld (
- //// input logic Clk, Reset, Load,
- //// input logic [127:0] D,
- //// output logic [127:0] Dout
- //// );
- ////
- //// always_ff @ (posedge Clk)
- //// begin
- //// if (Reset) //notice, this is a sycnrhonous reset, which is recommended on the FPGA
- //// Dout <= 128'b0;
- //// else if (Load)
- //// Dout <= D;
- //// end
- ////endmodule
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