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Apr 23rd, 2018
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VHDL 0.43 KB | None | 0 0
  1. --Compare-Logic--
  2. library ieee;
  3. use ieee.std_logic_1164.all;
  4. use ieee.numeric_std.all;
  5. use work.all;
  6.  
  7. entity compare_logic is
  8. port(
  9.     tm_alarm, tm_watch : in std_logic_vector(15 downto 0);
  10.     alarm : out std_logic
  11. );
  12. end;
  13.  
  14. architecture behavioral of compare_logic is
  15. begin
  16.     process(tm_watch)
  17.     begin
  18.             alarm <= '0';
  19.         if tm_alarm = tm_watch then
  20.             alarm <= '1';
  21.         else
  22.             alarm <='0';
  23.         end if;
  24.     end process;
  25. end;
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