Advertisement
Guest User

Untitled

a guest
Jun 18th, 2018
63
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
VHDL 0.55 KB | None | 0 0
  1. entity JohnsonCounter is
  2.     generic ( n : integer := 4);
  3.  
  4.     port (
  5.         clock : in std_logic;
  6.         reset : in std_logic;
  7.         output : out std_logic_vector(n-1 to 0) := (others => '0');
  8.     );
  9. end entity;
  10.  
  11. architecture Behaviour of JohnsonCounter is
  12.  
  13. begin
  14.     counter : process(clock, reset) is
  15.         if reset = '1' then
  16.             output <= (others => '0');
  17.         elsif rising_edge(clock) then
  18.             output(0) <= not output(n-1);
  19.  
  20.             looper : for i in (n-1) downto 1 loop
  21.                 output(i) <= output(i-1);
  22.             end loop looper;
  23.         end if;
  24.     end process counter;
  25. end architecture;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement