//
// CountDown Timer
//


module testbench2();

    // Device under test I/O
    logic clk, reset;
    logic [4:0] therapyDuration;
    logic [5:0] SEC;
    logic [4:0] MIN;

    //device under test
    countDownTimer countDownTimer(clk, reset, therapyDuration, SEC, MIN);

    initial
        forever begin
            clk=0; #2; clk=1; #2;
        end

    initial begin
        therapyDuration = 5'd30;
        reset = 1;
        #30;
        reset = 0;
        #35000;
    end

endmodule



module countDownTimer(input logic clk, reset,
                      input logic SWITCH,
                      input logic PAUSE,
                      input logic [4:0] therapyDuration,
                      output logic [5:0] SEC,
                      output logic [4:0] MIN);

    //CLK frequency 4Hz

    //MAIN CLK COUNTER //
    logic rst_countMainClk;
    logic [31:0] countClk;
    counter32bit countMainClk(clk, rst_countMainClk, countClk);
    assign rst_countMainClk = reset | (countClk == 32'd3); //clk_f - 1 = 4-1
    //assign rst_countMainClk = reset | (countClk == 32'd49_999_999)

    //SECOND TIMER //
    logic enSEC;
    assign enSEC = (countClk== 32'd3);
    //assign enSEC = (countClk== 32'd49_999_999);

    always_ff @(posedge clk)
        if(reset) SEC <= 6'd0;
        else if(enSEC)
        begin
            if( (SEC == 6'd0) ) SEC <= 6'd59;
            else                      SEC <= SEC - 1'b1;
        end

    //MINUTE TIMER //
    logic enMIN;
    assign enMIN = (SEC == 6'd0) & enSEC;

    always_ff @(posedge clk)
        if(reset)        MIN <= therapyDuration;
        else if(enMIN)  MIN <= MIN - 1'b1;

endmodule



countDownTimer_FSM(input logic SWITCH, STOP, COUNT_END, PAUSE, PAUSE_END,
                         output logic IDLE_state, COUNT_state, PAUSE_state, END_state);

    typedef enum logic [1:0] {S0,S1,S2,S3} statetype;
    statetype state, nextstate;

    //state register
    always_ff @(posedge clk, posedge reset)
        if(reset) state <= S0;          //reset to IDLE state
        else      state <= nextstate;

    //next state logic
    always_comb
        case(state)
            //IDLE STATE
            S0: if(SWITCH) nextstate = S1;
                 else           nextstate = S0;
            //COUNT STATE
            S1: if(PAUSE)                   nextstate = S2;
                 else if(STOP | COUNT_END) nextstate = S3;
                 else                           neststate = S1;
            //PAUSE STATE
            S2: if(SWITCH)                  nextstate = S1;
                 else if(STOP & PAUSE_END) nextstate = S3
                 else                               nextstate = S2;
            //END STATE
            S3: nextstate = S0;

            default: nextstate = S0;
        endcase

    //output logic
    assign IDLE_state = (state == S0);
    assign COUNT_state = (state == S1);
    assign PAUSE_state = (state == S2);
    assign END_state = (state == S3);

endmodule



module counter32bit(input logic clk, reset,
                          output logic [31:0] q);

    always_ff @(posedge clk)
        if(reset)   q <= 0;
        else            q <= q + 1'b1;

endmodule


/*
        R
clk     0   1   2   3   4   5   6   1   2   3   4   5   6   1
count   0   0   1   2   3   4   0   0   1   2   3   4   0   0
EN                              EN                      EN
reset                           r                       r
*/

/*

50MHz = 50,000,000 clk cycles
en  = (count == 49,999,998)
rst = (count == 49,999,999)


6Hz = 6 clk cycles
en  = (count == 4) or (count == clkcyles-2)
rst = (count == 5) or (count == clkcyles-1)

*/