library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;

entity porovnaj is
    port(in1 : in bit_vector(7 downto 0);
         in2 : in bit_vector(7 downto 0);
         ci : out bit);
end entity porovnaj;

architecture porovnavanie of porovnaj is
  begin
 --  ci <= '1' when in1(7) < in2(7);
process (in1,in2)
  begin
    if (in1(7 downto 1)< in2(7 downto 1)) then
      ci <= '1';
    else
      ci <= '0';
end if;
end process;


 -- if (in1(7) < in2(7)) then
  --    ci<='1';
  --else
   --   ci<='0';
  --end if ;

end architecture porovnavanie;

  -- testovacia entita
entity TESTT is
end TESTT;

-- architektura testovacej entity
architecture testuj of TESTT is
  component porovnaj is
    port(in1 : in bit_vector(7 downto 0);
         in2 : in bit_vector(7 downto 0);
         ci : out bit);
end component porovnaj;

signal vstup1, vstup2 : bit_vector(7 downto 0);
signal vystup : bit;
for porovnavaniee : porovnaj use entity work.porovnaj(porovnavanie);
  begin

porovnavaniee : porovnaj
  port map(in1=>vstup1, in2=>vstup2, ci=>vystup);

  T01 : vstup1 <= "10000001" after 10 ns, "00000001" after 20 ns, "10000001" after 30 ns, "00000001" after 40 ns;
  T02 : vstup2 <= "00000001" after 10 ns, "10000001" after 20 ns, "00000001" after 30 ns, "10000001" after 40 ns;

end architecture testuj;