%This paper talks about lambda-calculus and monads, which is key for
% functional programming used in functional languages such as
% haskell and also things like DDE.
@INPROCEEDINGS{moggi-1989,
author={E. Moggi},
booktitle={[1989] Proceedings. Fourth Annual Symposium on Logic in Computer Science},
title={Computational lambda-calculus and monads},
year={1989},
pages={14-23},
keywords={formal languages;formal logic;βη-conversion;λ-calculus;categorical semantics;computational lambda-calculus;equivalence of programs;mathematical tool;monads;programming languages;prove;Calculus;Computer languages;Computer science;Contracts;Logic programming;Mathematical model;Mathematical programming;Reasoning about programs},
doi={10.1109/LICS.1989.39155},
month={Jun},}
}

% This paper explains how to do a miss-under-miss cache architecture so as
% to minimize or almost completely eliminate cache miss penalty in a simple
% isa.
@inproceedings{kroft-1981,
  title={Lockup-free instruction fetch/prefetch cache organization},
  author={Kroft, David},
  booktitle={Proceedings of the 8th annual symposium on Computer Architecture},
  pages={81--87},
  year={1981},
  organization={IEEE Computer Society Press}
}

% This paper surveys prior works on different non-blocking caches and seperates
% four main design choices and discusses each method's potential speedup.
@article{belayneh-1996,
  title={A discussion on non-blocking/lockup-free caches},
  author={Belayneh, Samson and Kaeli, David R},
  journal={ACM SIGARCH Computer Architecture News},
  volume={24},
  number={3},
  pages={18--25},
  year={1996},
  publisher={ACM}
}

% This article covers different efforts to create other Demand-Driven and
% Data-Driven architectures and covers a lot of relationships between the
% concepts of Data Flow, Control Flow, and reduction.  This paper instead
% refers to Demand-driven as Control flow, though we are aiming to ignore this.
@article{treleaven-1982,
  title={Data-driven and demand-driven computer architecture},
  author={Treleaven, Philip C and Brownbridge, David R and Hopkins, Richard P},
  journal={ACM Computing Surveys (CSUR)},
  volume={14},
  number={1},
  pages={93--143},
  year={1982},
  publisher={ACM}
}
% This paper describes a microarchitecture that performs store/loads
% without using a store queue and uses a form of speculative memory bypassing
% to replace the store queue.
@inproceedings{sha-2006,
  title={Nosq: Store-load communication without a store queue},
  author={Sha, Tingting and Martin, Milo MK and Roth, Amir},
  booktitle={Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International Symposium on},
  pages={285--296},
  year={2006},
  organization={IEEE}
}

% The Alpha 21264 uses a speculative store buffer that can be used to repair
% mispeculations by squashing earlier instructions with later ones. This is similar
% to the original implementation of a store buffer.
@ARTICLE{kessler-1999,
author={R. E. Kessler},
journal={IEEE Micro},
title={The Alpha 21264 microprocessor},
year={1999},
volume={19},
number={2},
pages={24-36},
keywords={microprocessor chips;Alpha 21264 microprocessor;computational performance;data mining;high performance standard;medical imaging;real-time visual computing;Clocks;Data mining;High performance computing;Image databases;Microarchitecture;Microprocessors;Out of order;Robustness;Spatial databases;Visual databases},
doi={10.1109/40.755465},
ISSN={0272-1732},
month={Mar},}

% This paper outlines a lot of the work done on trace processors.
% Traces use both control flow and data flow heirarchy to distribute
% execution resources based on trace boundaries and make predictions
% based on traces instead of individual instructions
@inproceedings{rotenberg-1997,
  title={Trace processors},
  author={Rotenberg, Eric and Jacobson, Quinn and Sazeides, Yiannakis and Smith, Jim},
  booktitle={Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture},
  pages={138--148},
  year={1997},
  organization={IEEE Computer Society}
}

% This paper evaluates several different cache coherence protocols after outlining
% their specific implementations that are all hardware-based.
@article{archibald-1986,
  title={Cache coherence protocols: Evaluation using a multiprocessor simulation model},
  author={Archibald, James and Baer, Jean-Loup},
  journal={ACM Transactions on Computer Systems (TOCS)},
  volume={4},
  number={4},
  pages={273--298},
  year={1986},
  publisher={ACM}
}

% This paper looks at some of the weaknesses of the Manchester Dataflow
% Machine and how it handles a lot of these weaknesses along with a
% few other design challenges.
@article{gurd-1987,
  title={Performance issues in dataflow machines},
  author={Gurd, John and Bohm, Wim and Teo, Yong Meng},
  journal={Future Generation Computer Systems},
  volume={3},
  number={4},
  pages={285--297},
  year={1987},
  publisher={Elsevier}
}

% This surveys different alcorithms for parallel memory access
% on machines with have shared memory, including a shared
% LLC.
@ARTICLE{nitzberg-1991,
author={B. Nitzberg and V. Lo},
journal={Computer},
title={Distributed shared memory: a survey of issues and algorithms},
year={1991},
volume={24},
number={8},
pages={52-60},
keywords={data handling;distributed processing;storage management;DSM;coherence protocol;coherence semantics;data access;data location;distributed shared memory;granularity;heterogeneity;memory coherence;memory design choices;memory management;process synchronization;replacement strategy;scalability;thrashing;Data handling;Distributed computing;Memory management},
doi={10.1109/2.84877},
ISSN={0018-9162},
month={Aug},}

% This paper surveys different cache coherence schemes for
% multiprocessors.
@article{stenstrom-1990,
  title={A survey of cache coherence schemes for multiprocessors},
  author={Stenstrom, Per},
  journal={Computer},
  volume={23},
  number={6},
  pages={12--24},
  year={1990},
  publisher={IEEE}
}