pulser_solo

LIBRARY ieee;
use ieee.numeric_std.all;
use IEEE.std_logic_1164.all;

ENTITY pulser_solo IS
    generic (
        max_step_value : integer
    );
    PORT(
            rst                     :   in  std_logic;
            clk                     :   in  std_logic;

            clear                   :   in std_logic;

            current_step            :   in  integer range 0 to max_step_value;

            offset                  :   in  integer range 0 to max_step_value;
            pulse_length            :   in  integer range 0 to max_step_value;

            output                  :   out std_logic
        );
END ENTITY pulser_solo;

ARCHITECTURE behavioural OF pulser_solo IS

begin

    pulse : process (rst, clk) is
    begin
        if rst = '1' then
            output <= '0';
        elsif rising_edge(clk) then
            if clear = '1' then
                output <= '0';
            elsif   current_step >= offset and
                    current_step < pulse_length + offset then

                output <= '1';
            else
                output <= '0';

            end if;
        end if;
    end process pulse;


end architecture behavioural;