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  1. --------------------------------------------------------------------------------
  2. Release 14.7 Trace (lin64)
  3. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  4.  
  5. /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n
  6. 3 -fastpaths -xml orpsoc_top.twx orpsoc_top.ncd -o orpsoc_top.twr
  7. orpsoc_top.pcf
  8.  
  9. Design file: orpsoc_top.ncd
  10. Physical constraint file: orpsoc_top.pcf
  11. Device,package,speed: xc7a100t,csg324,C,-2 (PRODUCTION 1.10 2013-10-13)
  12. Report level: verbose report
  13.  
  14. Environment Variable Effect
  15. -------------------- ------
  16. NONE No environment variables were set
  17. --------------------------------------------------------------------------------
  18.  
  19. INFO:Timing:2698 - No timing constraints found, doing default enumeration.
  20. INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
  21. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
  22. option. All paths that are not constrained will be reported in the
  23. unconstrained paths section(s) of the report.
  24. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
  25. a 50 Ohm transmission line loading model. For the details of this model,
  26. and for more information on accounting for different loading conditions,
  27. please see the device datasheet.
  28.  
  29.  
  30.  
  31. Data Sheet report:
  32. -----------------
  33. All values displayed in nanoseconds (ns)
  34.  
  35. Setup/Hold to clock sys_clk_pad_i
  36. -------------------+------------+------------+------------+------------+------------------+--------+
  37. |Max Setup to| Process |Max Hold to | Process | | Clock |
  38. Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
  39. -------------------+------------+------------+------------+------------+------------------+--------+
  40. cellram_data_io<0> | 5.096(R)| SLOW | -1.918(R)| FAST |wb_clk | 0.000|
  41. cellram_data_io<1> | 5.515(R)| SLOW | -2.217(R)| FAST |wb_clk | 0.000|
  42. cellram_data_io<2> | 5.705(R)| SLOW | -2.079(R)| FAST |wb_clk | 0.000|
  43. cellram_data_io<3> | 5.068(R)| SLOW | -1.788(R)| FAST |wb_clk | 0.000|
  44. cellram_data_io<4> | 6.257(R)| SLOW | -1.875(R)| FAST |wb_clk | 0.000|
  45. cellram_data_io<5> | 5.225(R)| SLOW | -1.875(R)| FAST |wb_clk | 0.000|
  46. cellram_data_io<6> | 5.421(R)| SLOW | -1.803(R)| FAST |wb_clk | 0.000|
  47. cellram_data_io<7> | 5.258(R)| SLOW | -1.832(R)| FAST |wb_clk | 0.000|
  48. cellram_data_io<8> | 5.431(R)| SLOW | -1.926(R)| FAST |wb_clk | 0.000|
  49. cellram_data_io<9> | 5.962(R)| SLOW | -2.051(R)| FAST |wb_clk | 0.000|
  50. cellram_data_io<10>| 5.492(R)| SLOW | -1.994(R)| FAST |wb_clk | 0.000|
  51. cellram_data_io<11>| 5.219(R)| SLOW | -1.753(R)| FAST |wb_clk | 0.000|
  52. cellram_data_io<12>| 5.445(R)| SLOW | -1.900(R)| FAST |wb_clk | 0.000|
  53. cellram_data_io<13>| 4.810(R)| SLOW | -1.950(R)| FAST |wb_clk | 0.000|
  54. cellram_data_io<14>| 5.318(R)| SLOW | -1.670(R)| FAST |wb_clk | 0.000|
  55. cellram_data_io<15>| 5.572(R)| SLOW | -1.738(R)| FAST |wb_clk | 0.000|
  56. gpio0_io<0> | 4.224(R)| SLOW | -1.927(R)| FAST |wb_clk | 0.000|
  57. gpio0_io<1> | 4.249(R)| SLOW | -1.941(R)| FAST |wb_clk | 0.000|
  58. gpio0_io<2> | 3.937(R)| SLOW | -1.824(R)| FAST |wb_clk | 0.000|
  59. gpio0_io<3> | 4.166(R)| SLOW | -1.915(R)| FAST |wb_clk | 0.000|
  60. gpio0_io<4> | 5.077(R)| SLOW | -2.041(R)| FAST |wb_clk | 0.000|
  61. gpio0_io<5> | 4.432(R)| SLOW | -1.979(R)| FAST |wb_clk | 0.000|
  62. gpio0_io<6> | 4.186(R)| SLOW | -1.921(R)| FAST |wb_clk | 0.000|
  63. gpio0_io<7> | 4.525(R)| SLOW | -2.064(R)| FAST |wb_clk | 0.000|
  64. rst_n_pad_i | 5.464(R)| SLOW | -2.243(R)| FAST |wb_clk | 0.000|
  65. uart0_srx_pad_i | 3.903(R)| SLOW | -1.776(R)| FAST |wb_clk | 0.000|
  66. -------------------+------------+------------+------------+------------+------------------+--------+
  67.  
  68. Clock sys_clk_pad_i to Pad
  69. -------------------+-----------------+------------+-----------------+------------+------------------+--------+
  70. |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
  71. Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
  72. -------------------+-----------------+------------+-----------------+------------+------------------+--------+
  73. cellram_adr_o<0> | 5.979(R)| SLOW | 1.913(R)| FAST |wb_clk | 0.000|
  74. cellram_adr_o<1> | 6.381(R)| SLOW | 2.164(R)| FAST |wb_clk | 0.000|
  75. cellram_adr_o<2> | 5.992(R)| SLOW | 1.956(R)| FAST |wb_clk | 0.000|
  76. cellram_adr_o<3> | 6.047(R)| SLOW | 1.985(R)| FAST |wb_clk | 0.000|
  77. cellram_adr_o<4> | 6.510(R)| SLOW | 2.224(R)| FAST |wb_clk | 0.000|
  78. cellram_adr_o<5> | 5.881(R)| SLOW | 1.944(R)| FAST |wb_clk | 0.000|
  79. cellram_adr_o<6> | 6.310(R)| SLOW | 2.117(R)| FAST |wb_clk | 0.000|
  80. cellram_adr_o<7> | 5.402(R)| SLOW | 1.645(R)| FAST |wb_clk | 0.000|
  81. cellram_adr_o<8> | 5.819(R)| SLOW | 1.945(R)| FAST |wb_clk | 0.000|
  82. cellram_adr_o<9> | 5.809(R)| SLOW | 1.880(R)| FAST |wb_clk | 0.000|
  83. cellram_adr_o<10> | 5.830(R)| SLOW | 1.958(R)| FAST |wb_clk | 0.000|
  84. cellram_adr_o<11> | 5.782(R)| SLOW | 1.857(R)| FAST |wb_clk | 0.000|
  85. cellram_adr_o<12> | 5.616(R)| SLOW | 1.748(R)| FAST |wb_clk | 0.000|
  86. cellram_adr_o<13> | 5.499(R)| SLOW | 1.747(R)| FAST |wb_clk | 0.000|
  87. cellram_adr_o<14> | 5.363(R)| SLOW | 1.676(R)| FAST |wb_clk | 0.000|
  88. cellram_adr_o<15> | 5.514(R)| SLOW | 1.716(R)| FAST |wb_clk | 0.000|
  89. cellram_adr_o<16> | 5.244(R)| SLOW | 1.591(R)| FAST |wb_clk | 0.000|
  90. cellram_adr_o<17> | 5.506(R)| SLOW | 1.724(R)| FAST |wb_clk | 0.000|
  91. cellram_adr_o<18> | 6.003(R)| SLOW | 1.985(R)| FAST |wb_clk | 0.000|
  92. cellram_adr_o<19> | 6.110(R)| SLOW | 1.970(R)| FAST |wb_clk | 0.000|
  93. cellram_adr_o<20> | 6.065(R)| SLOW | 1.991(R)| FAST |wb_clk | 0.000|
  94. cellram_adr_o<21> | 5.369(R)| SLOW | 1.633(R)| FAST |wb_clk | 0.000|
  95. cellram_adr_o<22> | 6.376(R)| SLOW | 2.177(R)| FAST |wb_clk | 0.000|
  96. cellram_adv_n_o | 5.511(R)| SLOW | 1.714(R)| FAST |wb_clk | 0.000|
  97. cellram_ce_n_o | 5.498(R)| SLOW | 1.732(R)| FAST |wb_clk | 0.000|
  98. cellram_cre_o | 5.498(R)| SLOW | 1.674(R)| FAST |wb_clk | 0.000|
  99. cellram_data_io<0> | 10.006(R)| SLOW | 1.755(R)| FAST |wb_clk | 0.000|
  100. cellram_data_io<1> | 10.103(R)| SLOW | 1.776(R)| FAST |wb_clk | 0.000|
  101. cellram_data_io<2> | 10.238(R)| SLOW | 1.733(R)| FAST |wb_clk | 0.000|
  102. cellram_data_io<3> | 9.882(R)| SLOW | 1.690(R)| FAST |wb_clk | 0.000|
  103. cellram_data_io<4> | 9.855(R)| SLOW | 1.699(R)| FAST |wb_clk | 0.000|
  104. cellram_data_io<5> | 9.291(R)| SLOW | 1.511(R)| FAST |wb_clk | 0.000|
  105. cellram_data_io<6> | 9.512(R)| SLOW | 1.667(R)| FAST |wb_clk | 0.000|
  106. cellram_data_io<7> | 9.631(R)| SLOW | 1.606(R)| FAST |wb_clk | 0.000|
  107. cellram_data_io<8> | 10.813(R)| SLOW | 1.860(R)| FAST |wb_clk | 0.000|
  108. cellram_data_io<9> | 10.958(R)| SLOW | 1.861(R)| FAST |wb_clk | 0.000|
  109. cellram_data_io<10>| 11.212(R)| SLOW | 1.843(R)| FAST |wb_clk | 0.000|
  110. cellram_data_io<11>| 10.102(R)| SLOW | 1.721(R)| FAST |wb_clk | 0.000|
  111. cellram_data_io<12>| 8.896(R)| SLOW | 1.562(R)| FAST |wb_clk | 0.000|
  112. cellram_data_io<13>| 9.136(R)| SLOW | 1.633(R)| FAST |wb_clk | 0.000|
  113. cellram_data_io<14>| 9.252(R)| SLOW | 1.579(R)| FAST |wb_clk | 0.000|
  114. cellram_data_io<15>| 9.169(R)| SLOW | 1.565(R)| FAST |wb_clk | 0.000|
  115. cellram_lb_n_o | 5.868(R)| SLOW | 1.888(R)| FAST |wb_clk | 0.000|
  116. cellram_oe_n_o | 6.267(R)| SLOW | 2.116(R)| FAST |wb_clk | 0.000|
  117. cellram_ub_n_o | 6.029(R)| SLOW | 1.991(R)| FAST |wb_clk | 0.000|
  118. cellram_we_n_o | 5.571(R)| SLOW | 1.747(R)| FAST |wb_clk | 0.000|
  119. gpio0_io<0> | 5.752(R)| SLOW | 1.792(R)| FAST |wb_clk | 0.000|
  120. gpio0_io<1> | 5.753(R)| SLOW | 1.732(R)| FAST |wb_clk | 0.000|
  121. gpio0_io<2> | 5.753(R)| SLOW | 1.711(R)| FAST |wb_clk | 0.000|
  122. gpio0_io<3> | 5.650(R)| SLOW | 1.612(R)| FAST |wb_clk | 0.000|
  123. gpio0_io<4> | 6.455(R)| SLOW | 2.084(R)| FAST |wb_clk | 0.000|
  124. gpio0_io<5> | 6.506(R)| SLOW | 1.918(R)| FAST |wb_clk | 0.000|
  125. gpio0_io<6> | 5.823(R)| SLOW | 1.823(R)| FAST |wb_clk | 0.000|
  126. gpio0_io<7> | 5.897(R)| SLOW | 1.734(R)| FAST |wb_clk | 0.000|
  127. uart0_stx_pad_o | 7.950(R)| SLOW | 2.729(R)| FAST |wb_clk | 0.000|
  128. -------------------+-----------------+------------+-----------------+------------+------------------+--------+
  129.  
  130. Clock to Setup on destination clock sys_clk_pad_i
  131. ---------------+---------+---------+---------+---------+
  132. | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
  133. Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
  134. ---------------+---------+---------+---------+---------+
  135. sys_clk_pad_i | 13.480| | | |
  136. ---------------+---------+---------+---------+---------+
  137.  
  138.  
  139. Analysis completed Tue Apr 15 10:52:25 2014
  140. --------------------------------------------------------------------------------
  141.  
  142. Trace Settings:
  143. -------------------------
  144. Trace Settings
  145.  
  146. Peak Memory Usage: 865 MB
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