cursofpgavhdl

mux_4x1

Jul 30th, 2020
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  1. -- PROJETO: mux_4x1
  2. -- ENTRADA A, B, C, D, s1, s0 (tipo bit)
  3. -- SAIDA: S (tipo bit)
  4. -- AUTORES: MARCOS MEIRA, JOAO VITOR, SALLATIEL FERNANDES
  5. -- DATA: 22/06/2020
  6. ----------------------------------------------------------
  7. Entity mux_4x1 is
  8. Port(A, B, C, D : IN BIT;
  9.      s1, s0 : IN BIT;
  10.               S : OUT BIT);
  11. end mux_4x1;
  12. ----------------------------------------------------------
  13. Architecture arquitetura of mux_4x1 is
  14. begin
  15.     S <= ((NOT s1)  AND (NOT s0) AND (A)) OR -- 00
  16.           ((NOT s1) AND (s0)         AND (B)) OR -- 01
  17.           ((s1)     AND (NOT s0) AND (C)) OR -- 10
  18.           ((s1)     AND (s0)         AND (D));   -- 11
  19. end arquitetura;
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