// Benchmark "ISCAS89/s27" written by ABC on Fri Jan 17 17:55:38 2020

module \ISCAS89/s27  ( clock,
    G0, G1, G2, G3,
    G17  );
  input  clock;
  input  G0, G1, G2, G3;
  output G17;
  reg [2:0]state;
  wire new_G14_, new_G8_, new_G15_, new_G16_, new_G9_, new_G12_, n12, n17,
    n22;
  assign new_G14_ = ~G0;
  assign G17 = ~n17;
  assign new_G8_ = new_G14_ & state[1];
  assign new_G15_ = new_G12_ | new_G8_;
  assign new_G16_ = G3 | new_G8_;
  assign new_G9_ = ~new_G16_ | ~new_G15_;
  assign n12 = ~new_G14_ & ~n17;
  assign n17 = ~state[2] & ~new_G9_;
  assign new_G12_ = ~G1 & ~state[0];
  assign n22 = ~G2 & ~new_G12_;
  always @ (posedge clock) begin
    state[2]<=n12;
    state[1]<=n17;
    state[0]<=n22;
  end
endmodule