Task Lola II

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:         IS Enterpeises
// Engineer:        Letuchiy S.V.
//
// Create Date:    21:38:20 07/06/2019
// Design Name:      RunStiveRun
// Module Name:    RunStive
// Project Name:   Stive
// Target Devices: 9572 CPLD
// Tool versions:  ISE 14.7
// Description:      Shifter filler
//
// Dependencies:   None
//
// Revision:         001:1234:9347
// Revision 0.01 - File Created
// Additional Comments: None
//
//////////////////////////////////////////////////////////////////////////////////
module RunStive #(parameter DIGINIT = 21, DIGITA = DIGINIT + 3)                     // 21
(
    input  clk,
    output [3:0]row
);
// 25 wires.
wire [DIGITA:0]add;
//vwire [2:0]add_stp;

// Register counter.
reg  [DIGITA:0]RG = {(DIGINIT + 4){1'b0}};
// Register shifter
reg [3:0]rowGO = 4'b0000;
reg [3:0]rWW = 4'b0000;

assign row[3:0] = ~rWW[3:0];

assign add[DIGITA:0] = RG[DIGITA:0] + 1'b1;

always@(posedge clk) begin

            if(RG[DIGITA:0] == {{(DIGINIT + 2){1'b0}},{2'b10}}) begin

                if(rowGO[3:0] == 4'b0000) begin
                    rowGO[3:0] <= 4'b0001;
                    rWW <= rWW[3:0] + rowGO[3:0];
                end
                    else begin
                        // Shift one step left.
                        rowGO[3:0] <= rowGO[3:0] << 1'b1;
                        rWW <= rWW[3:0] + rowGO[3:0];

                        if(rWW[3:0] == 4'b1111) begin
                            rowGO[3:0] <= 4'b0000;
                            rWW[3:0] <= 4'b0000;
                        end

                    end

            end

            RG[DIGITA:0] <= add[DIGITA:0];
end

endmodule