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Task Lola II

akatla Jul 8th, 2019 78 Never
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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:         IS Enterpeises
  4. // Engineer:        Letuchiy S.V.
  5. //
  6. // Create Date:    21:38:20 07/06/2019
  7. // Design Name:      RunStiveRun
  8. // Module Name:    RunStive
  9. // Project Name:   Stive
  10. // Target Devices: 9572 CPLD
  11. // Tool versions:  ISE 14.7
  12. // Description:      Shifter filler
  13. //
  14. // Dependencies:   None
  15. //
  16. // Revision:         001:1234:9347
  17. // Revision 0.01 - File Created
  18. // Additional Comments: None
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module RunStive #(parameter DIGINIT = 21, DIGITA = DIGINIT + 3)                     // 21
  22. (  
  23.     input  clk,
  24.     output [3:0]row
  25. );
  26. // 25 wires.
  27. wire [DIGITA:0]add;
  28. //vwire [2:0]add_stp;
  29.  
  30. // Register counter.
  31. reg  [DIGITA:0]RG = {(DIGINIT + 4){1'b0}};
  32. // Register shifter
  33. reg [3:0]rowGO = 4'b0000;
  34. reg [3:0]rWW = 4'b0000;
  35.  
  36. assign row[3:0] = ~rWW[3:0];
  37.  
  38. assign add[DIGITA:0] = RG[DIGITA:0] + 1'b1;
  39.  
  40. always@(posedge clk) begin
  41.            
  42.             if(RG[DIGITA:0] == {{(DIGINIT + 2){1'b0}},{2'b10}}) begin          
  43.                        
  44.                 if(rowGO[3:0] == 4'b0000) begin
  45.                     rowGO[3:0] <= 4'b0001;
  46.                     rWW <= rWW[3:0] + rowGO[3:0];
  47.                 end
  48.                     else begin
  49.                         // Shift one step left.
  50.                         rowGO[3:0] <= rowGO[3:0] << 1'b1;
  51.                         rWW <= rWW[3:0] + rowGO[3:0];
  52.  
  53.                         if(rWW[3:0] == 4'b1111) begin
  54.                             rowGO[3:0] <= 4'b0000;
  55.                             rWW[3:0] <= 4'b0000;
  56.                         end
  57.  
  58.                     end
  59.                                    
  60.             end
  61.            
  62.             RG[DIGITA:0] <= add[DIGITA:0];
  63. end
  64.  
  65. endmodule
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