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- --18.01.2019 Igor Kojic
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- entity dec2to4 is
- Port (
- y: in std_logic_vector(1 downto 0);
- x: out std_logic_vector(3 downto 0);
- ei: in std_logic
- );
- end dec2to4;
- architecture Behavioral of dec2to4 is
- begin
- decoder: process (y,ei) is
- begin
- if(ei = '1')then
- if (y(1) = '0' and y(0) = '0') then
- x(0) <= '1';
- else
- x(0) <= '0';
- end if;
- if (y(1) = '0' and y(0) = '1') then
- x(1) <= '1';
- else
- x(1) <= '0';
- end if;
- if (y(1) = '1' and y(0) = '0') then
- x(2) <= '1';
- else
- x(2) <= '0';
- end if;
- if (y(1) = '1' and y(0) = '1') then
- x(3) <= '1';
- else
- x(3) <= '0';
- end if;
- else
- x<= "0000";
- end if;
- end process;
- end Behavioral;
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