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  1. --- build_dir/linux-brcm47xx/linux-2.6.32.9/drivers/ssb/scan_old.c  2010-02-23 18:38:51.000000000 +0300
  2. +++ build_dir/linux-brcm47xx/linux-2.6.32.9/drivers/ssb/scan_old1.c 2010-03-20 02:34:09.000000000 +0300
  3. @@ -1,439 +1,808 @@
  4. -/*
  5. - * Sonics Silicon Backplane
  6. - * Bus scanning
  7. - *
  8. - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
  9. - * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  10. - * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  11. - * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  12. - * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  13. - * Copyright (C) 2006 Broadcom Corporation.
  14. - *
  15. - * Licensed under the GNU/GPL. See COPYING for details.
  16. - */
  17. -
  18. -#include <linux/ssb/ssb.h>
  19. -#include <linux/ssb/ssb_regs.h>
  20. -#include <linux/pci.h>
  21. -#include <linux/io.h>
  22. -
  23. -#include <pcmcia/cs_types.h>
  24. -#include <pcmcia/cs.h>
  25. -#include <pcmcia/cistpl.h>
  26. -#include <pcmcia/ds.h>
  27. -
  28. -#include "ssb_private.h"
  29. -
  30. -
  31. -const char *ssb_core_name(u16 coreid)
  32. -{
  33. -   switch (coreid) {
  34. -   case SSB_DEV_CHIPCOMMON:
  35. -       return "ChipCommon";
  36. -   case SSB_DEV_ILINE20:
  37. -       return "ILine 20";
  38. -   case SSB_DEV_SDRAM:
  39. -       return "SDRAM";
  40. -   case SSB_DEV_PCI:
  41. -       return "PCI";
  42. -   case SSB_DEV_MIPS:
  43. -       return "MIPS";
  44. -   case SSB_DEV_ETHERNET:
  45. -       return "Fast Ethernet";
  46. -   case SSB_DEV_V90:
  47. -       return "V90";
  48. -   case SSB_DEV_USB11_HOSTDEV:
  49. -       return "USB 1.1 Hostdev";
  50. -   case SSB_DEV_ADSL:
  51. -       return "ADSL";
  52. -   case SSB_DEV_ILINE100:
  53. -       return "ILine 100";
  54. -   case SSB_DEV_IPSEC:
  55. -       return "IPSEC";
  56. -   case SSB_DEV_PCMCIA:
  57. -       return "PCMCIA";
  58. -   case SSB_DEV_INTERNAL_MEM:
  59. -       return "Internal Memory";
  60. -   case SSB_DEV_MEMC_SDRAM:
  61. -       return "MEMC SDRAM";
  62. -   case SSB_DEV_EXTIF:
  63. -       return "EXTIF";
  64. -   case SSB_DEV_80211:
  65. -       return "IEEE 802.11";
  66. -   case SSB_DEV_MIPS_3302:
  67. -       return "MIPS 3302";
  68. -   case SSB_DEV_USB11_HOST:
  69. -       return "USB 1.1 Host";
  70. -   case SSB_DEV_USB11_DEV:
  71. -       return "USB 1.1 Device";
  72. -   case SSB_DEV_USB20_HOST:
  73. -       return "USB 2.0 Host";
  74. -   case SSB_DEV_USB20_DEV:
  75. -       return "USB 2.0 Device";
  76. -   case SSB_DEV_SDIO_HOST:
  77. -       return "SDIO Host";
  78. -   case SSB_DEV_ROBOSWITCH:
  79. -       return "Roboswitch";
  80. -   case SSB_DEV_PARA_ATA:
  81. -       return "PATA";
  82. -   case SSB_DEV_SATA_XORDMA:
  83. -       return "SATA XOR-DMA";
  84. -   case SSB_DEV_ETHERNET_GBIT:
  85. -       return "GBit Ethernet";
  86. -   case SSB_DEV_PCIE:
  87. -       return "PCI-E";
  88. -   case SSB_DEV_MIMO_PHY:
  89. -       return "MIMO PHY";
  90. -   case SSB_DEV_SRAM_CTRLR:
  91. -       return "SRAM Controller";
  92. -   case SSB_DEV_MINI_MACPHY:
  93. -       return "Mini MACPHY";
  94. -   case SSB_DEV_ARM_1176:
  95. -       return "ARM 1176";
  96. -   case SSB_DEV_ARM_7TDMI:
  97. -       return "ARM 7TDMI";
  98. -   }
  99. -   return "UNKNOWN";
  100. -}
  101. -
  102. -static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
  103. -{
  104. -   u16 chipid_fallback = 0;
  105. -
  106. -   switch (pci_dev->device) {
  107. -   case 0x4301:
  108. -       chipid_fallback = 0x4301;
  109. -       break;
  110. -   case 0x4305 ... 0x4307:
  111. -       chipid_fallback = 0x4307;
  112. -       break;
  113. -   case 0x4403:
  114. -       chipid_fallback = 0x4402;
  115. -       break;
  116. -   case 0x4610 ... 0x4615:
  117. -       chipid_fallback = 0x4610;
  118. -       break;
  119. -   case 0x4710 ... 0x4715:
  120. -       chipid_fallback = 0x4710;
  121. -       break;
  122. -   case 0x4320 ... 0x4325:
  123. -       chipid_fallback = 0x4309;
  124. -       break;
  125. -   case PCI_DEVICE_ID_BCM4401:
  126. -   case PCI_DEVICE_ID_BCM4401B0:
  127. -   case PCI_DEVICE_ID_BCM4401B1:
  128. -       chipid_fallback = 0x4401;
  129. -       break;
  130. -   default:
  131. -       ssb_printk(KERN_ERR PFX
  132. -              "PCI-ID not in fallback list\n");
  133. -   }
  134. -
  135. -   return chipid_fallback;
  136. -}
  137. -
  138. -static u8 chipid_to_nrcores(u16 chipid)
  139. -{
  140. -   switch (chipid) {
  141. -   case 0x5365:
  142. -       return 7;
  143. -   case 0x4306:
  144. -       return 6;
  145. -   case 0x4310:
  146. -       return 8;
  147. -   case 0x4307:
  148. -   case 0x4301:
  149. -       return 5;
  150. -   case 0x4401:
  151. -   case 0x4402:
  152. -       return 3;
  153. -   case 0x4710:
  154. -   case 0x4610:
  155. -   case 0x4704:
  156. -       return 9;
  157. -   default:
  158. -       ssb_printk(KERN_ERR PFX
  159. -              "CHIPID not in nrcores fallback list\n");
  160. -   }
  161. -
  162. -   return 1;
  163. -}
  164. -
  165. -static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
  166. -              u16 offset)
  167. -{
  168. -   u32 lo, hi;
  169. -
  170. -   switch (bus->bustype) {
  171. -   case SSB_BUSTYPE_SSB:
  172. -       offset += current_coreidx * SSB_CORE_SIZE;
  173. -       break;
  174. -   case SSB_BUSTYPE_PCI:
  175. -       break;
  176. -   case SSB_BUSTYPE_PCMCIA:
  177. -       if (offset >= 0x800) {
  178. -           ssb_pcmcia_switch_segment(bus, 1);
  179. -           offset -= 0x800;
  180. -       } else
  181. -           ssb_pcmcia_switch_segment(bus, 0);
  182. -       lo = readw(bus->mmio + offset);
  183. -       hi = readw(bus->mmio + offset + 2);
  184. -       return lo | (hi << 16);
  185. -   case SSB_BUSTYPE_SDIO:
  186. -       offset += current_coreidx * SSB_CORE_SIZE;
  187. -       return ssb_sdio_scan_read32(bus, offset);
  188. -   }
  189. -   return readl(bus->mmio + offset);
  190. -}
  191. -
  192. -static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
  193. -{
  194. -   switch (bus->bustype) {
  195. -   case SSB_BUSTYPE_SSB:
  196. -       break;
  197. -   case SSB_BUSTYPE_PCI:
  198. -       return ssb_pci_switch_coreidx(bus, coreidx);
  199. -   case SSB_BUSTYPE_PCMCIA:
  200. -       return ssb_pcmcia_switch_coreidx(bus, coreidx);
  201. -   case SSB_BUSTYPE_SDIO:
  202. -       return ssb_sdio_scan_switch_coreidx(bus, coreidx);
  203. -   }
  204. -   return 0;
  205. -}
  206. -
  207. -void ssb_iounmap(struct ssb_bus *bus)
  208. -{
  209. -   switch (bus->bustype) {
  210. -   case SSB_BUSTYPE_SSB:
  211. -   case SSB_BUSTYPE_PCMCIA:
  212. -       iounmap(bus->mmio);
  213. -       break;
  214. -   case SSB_BUSTYPE_PCI:
  215. -#ifdef CONFIG_SSB_PCIHOST
  216. -       pci_iounmap(bus->host_pci, bus->mmio);
  217. -#else
  218. -       SSB_BUG_ON(1); /* Can't reach this code. */
  219. -#endif
  220. -       break;
  221. -   case SSB_BUSTYPE_SDIO:
  222. -       break;
  223. -   }
  224. -   bus->mmio = NULL;
  225. -   bus->mapped_device = NULL;
  226. -}
  227. -
  228. -static void __iomem *ssb_ioremap(struct ssb_bus *bus,
  229. -                unsigned long baseaddr)
  230. -{
  231. -   void __iomem *mmio = NULL;
  232. -
  233. -   switch (bus->bustype) {
  234. -   case SSB_BUSTYPE_SSB:
  235. -       /* Only map the first core for now. */
  236. -       /* fallthrough... */
  237. -   case SSB_BUSTYPE_PCMCIA:
  238. -       mmio = ioremap(baseaddr, SSB_CORE_SIZE);
  239. -       break;
  240. -   case SSB_BUSTYPE_PCI:
  241. -#ifdef CONFIG_SSB_PCIHOST
  242. -       mmio = pci_iomap(bus->host_pci, 0, ~0UL);
  243. -#else
  244. -       SSB_BUG_ON(1); /* Can't reach this code. */
  245. -#endif
  246. -       break;
  247. -   case SSB_BUSTYPE_SDIO:
  248. -       /* Nothing to ioremap in the SDIO case, just fake it */
  249. -       mmio = (void __iomem *)baseaddr;
  250. -       break;
  251. -   }
  252. -
  253. -   return mmio;
  254. -}
  255. -
  256. -static int we_support_multiple_80211_cores(struct ssb_bus *bus)
  257. -{
  258. -   /* More than one 802.11 core is only supported by special chips.
  259. -    * There are chips with two 802.11 cores, but with dangling
  260. -    * pins on the second core. Be careful and reject them here.
  261. -    */
  262. -
  263. -#ifdef CONFIG_SSB_PCIHOST
  264. -   if (bus->bustype == SSB_BUSTYPE_PCI) {
  265. -       if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
  266. -           bus->host_pci->device == 0x4324)
  267. -           return 1;
  268. -   }
  269. -#endif /* CONFIG_SSB_PCIHOST */
  270. -   return 0;
  271. -}
  272. -
  273. -int ssb_bus_scan(struct ssb_bus *bus,
  274. -        unsigned long baseaddr)
  275. -{
  276. -   int err = -ENOMEM;
  277. -   void __iomem *mmio;
  278. -   u32 idhi, cc, rev, tmp;
  279. -   int dev_i, i;
  280. -   struct ssb_device *dev;
  281. -   int nr_80211_cores = 0;
  282. -
  283. -   mmio = ssb_ioremap(bus, baseaddr);
  284. -   if (!mmio)
  285. -       goto out;
  286. -   bus->mmio = mmio;
  287. -
  288. -   err = scan_switchcore(bus, 0); /* Switch to first core */
  289. -   if (err)
  290. -       goto err_unmap;
  291. -
  292. -   idhi = scan_read32(bus, 0, SSB_IDHIGH);
  293. -   cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
  294. -   rev = (idhi & SSB_IDHIGH_RCLO);
  295. -   rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
  296. -
  297. -   bus->nr_devices = 0;
  298. -   if (cc == SSB_DEV_CHIPCOMMON) {
  299. -       tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
  300. -
  301. -       bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
  302. -       bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
  303. -               SSB_CHIPCO_REVSHIFT;
  304. -       bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
  305. -                   SSB_CHIPCO_PACKSHIFT;
  306. -       if (rev >= 4) {
  307. -           bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
  308. -                     SSB_CHIPCO_NRCORESSHIFT;
  309. -       }
  310. -       tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
  311. -       bus->chipco.capabilities = tmp;
  312. -   } else {
  313. -       if (bus->bustype == SSB_BUSTYPE_PCI) {
  314. -           bus->chip_id = pcidev_to_chipid(bus->host_pci);
  315. -           pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
  316. -                        &bus->chip_rev);
  317. -           bus->chip_package = 0;
  318. -       } else {
  319. -           bus->chip_id = 0x4710;
  320. -           bus->chip_rev = 0;
  321. -           bus->chip_package = 0;
  322. -       }
  323. -   }
  324. -   if (!bus->nr_devices)
  325. -       bus->nr_devices = chipid_to_nrcores(bus->chip_id);
  326. -   if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
  327. -       ssb_printk(KERN_ERR PFX
  328. -              "More than %d ssb cores found (%d)\n",
  329. -              SSB_MAX_NR_CORES, bus->nr_devices);
  330. -       goto err_unmap;
  331. -   }
  332. -   if (bus->bustype == SSB_BUSTYPE_SSB) {
  333. -       /* Now that we know the number of cores,
  334. -        * remap the whole IO space for all cores.
  335. -        */
  336. -       err = -ENOMEM;
  337. -       iounmap(mmio);
  338. -       mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
  339. -       if (!mmio)
  340. -           goto out;
  341. -       bus->mmio = mmio;
  342. -   }
  343. -
  344. -   /* Fetch basic information about each core/device */
  345. -   for (i = 0, dev_i = 0; i < bus->nr_devices; i++) {
  346. -       err = scan_switchcore(bus, i);
  347. -       if (err)
  348. -           goto err_unmap;
  349. -       dev = &(bus->devices[dev_i]);
  350. -
  351. -       idhi = scan_read32(bus, i, SSB_IDHIGH);
  352. -       dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
  353. -       dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
  354. -       dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
  355. -       dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
  356. -       dev->core_index = i;
  357. -       dev->bus = bus;
  358. -       dev->ops = bus->ops;
  359. -
  360. -       ssb_dprintk(KERN_INFO PFX
  361. -               "Core %d found: %s "
  362. -               "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
  363. -               i, ssb_core_name(dev->id.coreid),
  364. -               dev->id.coreid, dev->id.revision, dev->id.vendor);
  365. -
  366. -       switch (dev->id.coreid) {
  367. -       case SSB_DEV_80211:
  368. -           nr_80211_cores++;
  369. -           if (nr_80211_cores > 1) {
  370. -               if (!we_support_multiple_80211_cores(bus)) {
  371. -                   ssb_dprintk(KERN_INFO PFX "Ignoring additional "
  372. -                           "802.11 core\n");
  373. -                   continue;
  374. -               }
  375. -           }
  376. -           break;
  377. -       case SSB_DEV_EXTIF:
  378. -#ifdef CONFIG_SSB_DRIVER_EXTIF
  379. -           if (bus->extif.dev) {
  380. -               ssb_printk(KERN_WARNING PFX
  381. -                      "WARNING: Multiple EXTIFs found\n");
  382. -               break;
  383. -           }
  384. -           bus->extif.dev = dev;
  385. -#endif /* CONFIG_SSB_DRIVER_EXTIF */
  386. -           break;
  387. -       case SSB_DEV_CHIPCOMMON:
  388. -           if (bus->chipco.dev) {
  389. -               ssb_printk(KERN_WARNING PFX
  390. -                      "WARNING: Multiple ChipCommon found\n");
  391. -               break;
  392. -           }
  393. -           bus->chipco.dev = dev;
  394. -           break;
  395. -       case SSB_DEV_MIPS:
  396. -       case SSB_DEV_MIPS_3302:
  397. -#ifdef CONFIG_SSB_DRIVER_MIPS
  398. -           if (bus->mipscore.dev) {
  399. -               ssb_printk(KERN_WARNING PFX
  400. -                      "WARNING: Multiple MIPS cores found\n");
  401. -               break;
  402. -           }
  403. -           bus->mipscore.dev = dev;
  404. -#endif /* CONFIG_SSB_DRIVER_MIPS */
  405. -           break;
  406. -       case SSB_DEV_PCI:
  407. -       case SSB_DEV_PCIE:
  408. -#ifdef CONFIG_SSB_DRIVER_PCICORE
  409. -           if (bus->bustype == SSB_BUSTYPE_PCI) {
  410. -               /* Ignore PCI cores on PCI-E cards.
  411. -                * Ignore PCI-E cores on PCI cards. */
  412. -               if (dev->id.coreid == SSB_DEV_PCI) {
  413. -                   if (bus->host_pci->is_pcie)
  414. -                       continue;
  415. -               } else {
  416. -                   if (!bus->host_pci->is_pcie)
  417. -                       continue;
  418. -               }
  419. -           }
  420. -           if (bus->pcicore.dev) {
  421. -               ssb_printk(KERN_WARNING PFX
  422. -                      "WARNING: Multiple PCI(E) cores found\n");
  423. -               break;
  424. -           }
  425. -           bus->pcicore.dev = dev;
  426. -#endif /* CONFIG_SSB_DRIVER_PCICORE */
  427. -           break;
  428. -       default:
  429. -           break;
  430. -       }
  431. -
  432. -       dev_i++;
  433. -   }
  434. -   bus->nr_devices = dev_i;
  435. -
  436. -   err = 0;
  437. -out:
  438. -   return err;
  439. -err_unmap:
  440. -   ssb_iounmap(bus);
  441. -   goto out;
  442. -}
  443. +/*
  444. + * Sonics Silicon Backplane
  445. + * Bus scanning
  446. + *
  447. + * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
  448. + * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  449. + * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  450. + * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  451. + * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  452. + * Copyright (C) 2006 Broadcom Corporation.
  453. + *
  454. + * Licensed under the GNU/GPL. See COPYING for details.
  455. + */
  456. +
  457. +#include <linux/ssb/ssb.h>
  458. +#include <linux/ssb/ssb_regs.h>
  459. +#include <linux/pci.h>
  460. +#include <linux/io.h>
  461. +
  462. +#include <pcmcia/cs_types.h>
  463. +#include <pcmcia/cs.h>
  464. +#include <pcmcia/cistpl.h>
  465. +#include <pcmcia/ds.h>
  466. +
  467. +#include "ssb_private.h"
  468. +
  469. +
  470. +const char *ssb_core_name(u16 coreid)
  471. +{
  472. +   switch (coreid) {
  473. +   case SSB_DEV_CHIPCOMMON:
  474. +       return "ChipCommon";
  475. +   case SSB_DEV_ILINE20:
  476. +       return "ILine 20";
  477. +   case SSB_DEV_SDRAM:
  478. +       return "SDRAM";
  479. +   case SSB_DEV_PCI:
  480. +       return "PCI";
  481. +   case SSB_DEV_MIPS:
  482. +       return "MIPS";
  483. +   case SSB_DEV_ETHERNET:
  484. +       return "Fast Ethernet";
  485. +   case SSB_DEV_V90:
  486. +       return "V90";
  487. +   case SSB_DEV_USB11_HOSTDEV:
  488. +       return "USB 1.1 Hostdev";
  489. +   case SSB_DEV_ADSL:
  490. +       return "ADSL";
  491. +   case SSB_DEV_ILINE100:
  492. +       return "ILine 100";
  493. +   case SSB_DEV_IPSEC:
  494. +       return "IPSEC";
  495. +   case SSB_DEV_PCMCIA:
  496. +       return "PCMCIA";
  497. +   case SSB_DEV_INTERNAL_MEM:
  498. +       return "Internal Memory";
  499. +   case SSB_DEV_MEMC_SDRAM:
  500. +       return "MEMC SDRAM";
  501. +   case SSB_DEV_EXTIF:
  502. +       return "EXTIF";
  503. +   case SSB_DEV_80211:
  504. +       return "IEEE 802.11";
  505. +   case SSB_DEV_MIPS_3302:
  506. +       return "MIPS 3302";
  507. +   case SSB_DEV_USB11_HOST:
  508. +       return "USB 1.1 Host";
  509. +   case SSB_DEV_USB11_DEV:
  510. +       return "USB 1.1 Device";
  511. +   case SSB_DEV_USB20_HOST:
  512. +       return "USB 2.0 Host";
  513. +   case SSB_DEV_USB20_DEV:
  514. +       return "USB 2.0 Device";
  515. +   case SSB_DEV_SDIO_HOST:
  516. +       return "SDIO Host";
  517. +   case SSB_DEV_ROBOSWITCH:
  518. +       return "Roboswitch";
  519. +   case SSB_DEV_PARA_ATA:
  520. +       return "PATA";
  521. +   case SSB_DEV_SATA_XORDMA:
  522. +       return "SATA XOR-DMA";
  523. +   case SSB_DEV_ETHERNET_GBIT:
  524. +       return "GBit Ethernet";
  525. +   case SSB_DEV_PCIE:
  526. +       return "PCI-E";
  527. +   case SSB_DEV_MIMO_PHY:
  528. +       return "MIMO PHY";
  529. +   case SSB_DEV_SRAM_CTRLR:
  530. +       return "SRAM Controller";
  531. +   case SSB_DEV_MINI_MACPHY:
  532. +       return "Mini MACPHY";
  533. +   case SSB_DEV_ARM_1176:
  534. +       return "ARM 1176";
  535. +   case SSB_DEV_ARM_7TDMI:
  536. +       return "ARM 7TDMI";
  537. +   }
  538. +   return "UNKNOWN";
  539. +}
  540. +
  541. +static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
  542. +{
  543. +   u16 chipid_fallback = 0;
  544. +
  545. +   switch (pci_dev->device) {
  546. +   case 0x4301:
  547. +       chipid_fallback = 0x4301;
  548. +       break;
  549. +   case 0x4305 ... 0x4307:
  550. +       chipid_fallback = 0x4307;
  551. +       break;
  552. +   case 0x4403:
  553. +       chipid_fallback = 0x4402;
  554. +       break;
  555. +   case 0x4610 ... 0x4615:
  556. +       chipid_fallback = 0x4610;
  557. +       break;
  558. +   case 0x4710 ... 0x4715:
  559. +       chipid_fallback = 0x4710;
  560. +       break;
  561. +   case 0x4320 ... 0x4325:
  562. +       chipid_fallback = 0x4309;
  563. +       break;
  564. +   case PCI_DEVICE_ID_BCM4401:
  565. +   case PCI_DEVICE_ID_BCM4401B0:
  566. +   case PCI_DEVICE_ID_BCM4401B1:
  567. +       chipid_fallback = 0x4401;
  568. +       break;
  569. +   default:
  570. +       ssb_printk(KERN_ERR PFX
  571. +              "PCI-ID not in fallback list\n");
  572. +   }
  573. +
  574. +   return chipid_fallback;
  575. +}
  576. +
  577. +static u8 chipid_to_nrcores(u16 chipid)
  578. +{
  579. +   switch (chipid) {
  580. +   case 0x5365:
  581. +       return 7;
  582. +   case 0x4306:
  583. +       return 6;
  584. +   case 0x4310:
  585. +       return 8;
  586. +   case 0x4307:
  587. +   case 0x4301:
  588. +       return 5;
  589. +   case 0x4401:
  590. +   case 0x4402:
  591. +       return 3;
  592. +   case 0x4710:
  593. +   case 0x4610:
  594. +   case 0x4704:
  595. +       return 9;
  596. +   default:
  597. +       ssb_printk(KERN_ERR PFX
  598. +              "CHIPID not in nrcores fallback list\n");
  599. +   }
  600. +
  601. +   return 1;
  602. +}
  603. +
  604. +static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
  605. +              u16 offset)
  606. +{
  607. +   u32 lo, hi;
  608. +
  609. +   switch (bus->bustype) {
  610. +   case SSB_BUSTYPE_SSB:
  611. +       printk("asdf\n");
  612. +       offset += current_coreidx * SSB_CORE_SIZE;
  613. +       break;
  614. +   case SSB_BUSTYPE_PCI:
  615. +       break;
  616. +   case SSB_BUSTYPE_PCMCIA:
  617. +       if (offset >= 0x800) {
  618. +           ssb_pcmcia_switch_segment(bus, 1);
  619. +           offset -= 0x800;
  620. +       } else
  621. +           ssb_pcmcia_switch_segment(bus, 0);
  622. +       lo = readw(bus->mmio + offset);
  623. +       hi = readw(bus->mmio + offset + 2);
  624. +       return lo | (hi << 16);
  625. +   case SSB_BUSTYPE_SDIO:
  626. +       offset += current_coreidx * SSB_CORE_SIZE;
  627. +       return ssb_sdio_scan_read32(bus, offset);
  628. +   }
  629. +   printk("ssbread: %x\n", bus->mmio + offset);
  630. +   return readl(bus->mmio + offset);
  631. +}
  632. +
  633. +static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
  634. +{
  635. +   switch (bus->bustype) {
  636. +   case SSB_BUSTYPE_SSB:
  637. +       break;
  638. +   case SSB_BUSTYPE_PCI:
  639. +       return ssb_pci_switch_coreidx(bus, coreidx);
  640. +   case SSB_BUSTYPE_PCMCIA:
  641. +       return ssb_pcmcia_switch_coreidx(bus, coreidx);
  642. +   case SSB_BUSTYPE_SDIO:
  643. +       return ssb_sdio_scan_switch_coreidx(bus, coreidx);
  644. +   }
  645. +   return 0;
  646. +}
  647. +
  648. +void ssb_iounmap(struct ssb_bus *bus)
  649. +{
  650. +   switch (bus->bustype) {
  651. +   case SSB_BUSTYPE_SSB:
  652. +   case SSB_BUSTYPE_PCMCIA:
  653. +       iounmap(bus->mmio);
  654. +       break;
  655. +   case SSB_BUSTYPE_PCI:
  656. +#ifdef CONFIG_SSB_PCIHOST
  657. +       pci_iounmap(bus->host_pci, bus->mmio);
  658. +#else
  659. +       SSB_BUG_ON(1); /* Can't reach this code. */
  660. +#endif
  661. +       break;
  662. +   case SSB_BUSTYPE_SDIO:
  663. +       break;
  664. +   }
  665. +   bus->mmio = NULL;
  666. +   bus->mapped_device = NULL;
  667. +}
  668. +
  669. +static void __iomem *ssb_ioremap(struct ssb_bus *bus,
  670. +                unsigned long baseaddr)
  671. +{
  672. +   void __iomem *mmio = NULL;
  673. +
  674. +   switch (bus->bustype) {
  675. +   case SSB_BUSTYPE_SSB:
  676. +       /* Only map the first core for now. */
  677. +       /* fallthrough... */
  678. +   case SSB_BUSTYPE_PCMCIA:
  679. +       mmio = ioremap(baseaddr, SSB_CORE_SIZE);
  680. +       break;
  681. +   case SSB_BUSTYPE_PCI:
  682. +#ifdef CONFIG_SSB_PCIHOST
  683. +       mmio = pci_iomap(bus->host_pci, 0, ~0UL);
  684. +#else
  685. +       SSB_BUG_ON(1); /* Can't reach this code. */
  686. +#endif
  687. +       break;
  688. +   case SSB_BUSTYPE_SDIO:
  689. +       /* Nothing to ioremap in the SDIO case, just fake it */
  690. +       mmio = (void __iomem *)baseaddr;
  691. +       break;
  692. +   }
  693. +
  694. +   return mmio;
  695. +}
  696. +
  697. +static int we_support_multiple_80211_cores(struct ssb_bus *bus)
  698. +{
  699. +   /* More than one 802.11 core is only supported by special chips.
  700. +    * There are chips with two 802.11 cores, but with dangling
  701. +    * pins on the second core. Be careful and reject them here.
  702. +    */
  703. +
  704. +#ifdef CONFIG_SSB_PCIHOST
  705. +   if (bus->bustype == SSB_BUSTYPE_PCI) {
  706. +       if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
  707. +           bus->host_pci->device == 0x4324)
  708. +           return 1;
  709. +   }
  710. +#endif /* CONFIG_SSB_PCIHOST */
  711. +   return 0;
  712. +}
  713. +
  714. +int ssb_bus_scan1(struct ssb_bus *bus,
  715. +        unsigned long baseaddr)
  716. +{
  717. +   int err = -ENOMEM;
  718. +   void __iomem *mmio;
  719. +   u32 idhi, cc, rev, tmp;
  720. +   int dev_i, i;
  721. +   struct ssb_device *dev;
  722. +   int nr_80211_cores = 0;
  723. +
  724. +   mmio = ssb_ioremap(bus, baseaddr);
  725. +   if (!mmio)
  726. +       goto out;
  727. +   bus->mmio = mmio;
  728. +printk("s1\n");
  729. +   err = scan_switchcore(bus, 0); /* Switch to first core */
  730. +   if (err)
  731. +       goto err_unmap;
  732. +printk("s2\n");
  733. +   tmp=scan_read32(bus, 0, 0);
  734. +   printk("s2a: %x\n", tmp);
  735. +   idhi = scan_read32(bus, 0, SSB_IDHIGH);
  736. +   cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
  737. +   rev = (idhi & SSB_IDHIGH_RCLO);
  738. +   rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
  739. +printk("s3\n");
  740. +   bus->nr_devices = 0;
  741. +   if (cc == SSB_DEV_CHIPCOMMON) {
  742. +       tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
  743. +printk("s4\n");
  744. +       bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
  745. +       bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
  746. +               SSB_CHIPCO_REVSHIFT;
  747. +       bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
  748. +                   SSB_CHIPCO_PACKSHIFT;
  749. +       if (rev >= 4) {
  750. +           bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
  751. +                     SSB_CHIPCO_NRCORESSHIFT;
  752. +       }
  753. +       tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
  754. +       bus->chipco.capabilities = tmp;
  755. +   } else {
  756. +     printk("s5\n");
  757. +       if (bus->bustype == SSB_BUSTYPE_PCI) {
  758. +           bus->chip_id = pcidev_to_chipid(bus->host_pci);
  759. +           pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
  760. +                        &bus->chip_rev);
  761. +           bus->chip_package = 0;
  762. +       } else {
  763. +           bus->chip_id = 0x4710;
  764. +           bus->chip_rev = 0;
  765. +           bus->chip_package = 0;
  766. +       }
  767. +   }
  768. +   printk("s6\n");
  769. +   if (!bus->nr_devices)
  770. +       bus->nr_devices = chipid_to_nrcores(bus->chip_id);
  771. +   if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
  772. +       ssb_printk(KERN_ERR PFX
  773. +              "More than %d ssb cores found (%d)\n",
  774. +              SSB_MAX_NR_CORES, bus->nr_devices);
  775. +       goto err_unmap;
  776. +   }
  777. +   if (bus->bustype == SSB_BUSTYPE_SSB) {
  778. +     printk("s7\n");
  779. +       /* Now that we know the number of cores,
  780. +        * remap the whole IO space for all cores.
  781. +        */
  782. +       err = -ENOMEM;
  783. +       iounmap(mmio);
  784. +       mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
  785. +       if (!mmio)
  786. +           goto out;
  787. +       bus->mmio = mmio;
  788. +   }
  789. +
  790. +   /* Fetch basic information about each core/device */
  791. +   for (i = 0, dev_i = 0; i < bus->nr_devices; i++) {
  792. +     printk("s8: %i\n", i);
  793. +       err = scan_switchcore(bus, i);
  794. +       if (err)
  795. +           goto err_unmap;
  796. +       dev = &(bus->devices[dev_i]);
  797. +printk("s9\n");
  798. +       idhi = scan_read32(bus, i, SSB_IDHIGH);
  799. +       dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
  800. +       dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
  801. +       dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
  802. +       dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
  803. +       dev->core_index = i;
  804. +       dev->bus = bus;
  805. +       dev->ops = bus->ops;
  806. +
  807. +       ssb_printk(KERN_INFO PFX
  808. +               "Core %d found: %s "
  809. +               "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
  810. +               i, ssb_core_name(dev->id.coreid),
  811. +               dev->id.coreid, dev->id.revision, dev->id.vendor);
  812. +
  813. +       switch (dev->id.coreid) {
  814. +       case SSB_DEV_80211:
  815. +           nr_80211_cores++;
  816. +           if (nr_80211_cores > 1) {
  817. +               if (!we_support_multiple_80211_cores(bus)) {
  818. +                   ssb_dprintk(KERN_INFO PFX "Ignoring additional "
  819. +                           "802.11 core\n");
  820. +                   continue;
  821. +               }
  822. +           }
  823. +           break;
  824. +       case SSB_DEV_EXTIF:
  825. +#ifdef CONFIG_SSB_DRIVER_EXTIF
  826. +           if (bus->extif.dev) {
  827. +               ssb_printk(KERN_WARNING PFX
  828. +                      "WARNING: Multiple EXTIFs found\n");
  829. +               break;
  830. +           }
  831. +           bus->extif.dev = dev;
  832. +#endif /* CONFIG_SSB_DRIVER_EXTIF */
  833. +           break;
  834. +       case SSB_DEV_CHIPCOMMON:
  835. +           if (bus->chipco.dev) {
  836. +               ssb_printk(KERN_WARNING PFX
  837. +                      "WARNING: Multiple ChipCommon found\n");
  838. +               break;
  839. +           }
  840. +           bus->chipco.dev = dev;
  841. +           break;
  842. +       case SSB_DEV_MIPS:
  843. +       case SSB_DEV_MIPS_3302:
  844. +#ifdef CONFIG_SSB_DRIVER_MIPS
  845. +           if (bus->mipscore.dev) {
  846. +               ssb_printk(KERN_WARNING PFX
  847. +                      "WARNING: Multiple MIPS cores found\n");
  848. +               break;
  849. +           }
  850. +           bus->mipscore.dev = dev;
  851. +           printk("bus->mipscore.dev: %x\n",bus->mipscore.dev);
  852. +#endif /* CONFIG_SSB_DRIVER_MIPS */
  853. +           break;
  854. +       case SSB_DEV_PCI:
  855. +       case SSB_DEV_PCIE:
  856. +#ifdef CONFIG_SSB_DRIVER_PCICORE
  857. +           if (bus->bustype == SSB_BUSTYPE_PCI) {
  858. +               /* Ignore PCI cores on PCI-E cards.
  859. +                * Ignore PCI-E cores on PCI cards. */
  860. +               if (dev->id.coreid == SSB_DEV_PCI) {
  861. +                   if (bus->host_pci->is_pcie)
  862. +                       continue;
  863. +               } else {
  864. +                   if (!bus->host_pci->is_pcie)
  865. +                       continue;
  866. +               }
  867. +           }
  868. +           if (bus->pcicore.dev) {
  869. +               ssb_printk(KERN_WARNING PFX
  870. +                      "WARNING: Multiple PCI(E) cores found\n");
  871. +               break;
  872. +           }
  873. +           bus->pcicore.dev = dev;
  874. +#endif /* CONFIG_SSB_DRIVER_PCICORE */
  875. +           break;
  876. +       default:
  877. +           break;
  878. +       }
  879. +
  880. +       dev_i++;
  881. +       printk("s10\n");
  882. +   }
  883. +   bus->nr_devices = dev_i;
  884. +
  885. +   err = 0;
  886. +out:
  887. +   return err;
  888. +err_unmap:
  889. +   ssb_iounmap(bus);
  890. +   goto out;
  891. +}
  892. +
  893. +typedef u32 uint32;
  894. +
  895. +typedef volatile struct {
  896. +   uint32  chipid;         /* 0x0 */
  897. +   uint32  capabilities;
  898. +   uint32  corecontrol;        /* corerev >= 1 */
  899. +   uint32  bist;
  900. +
  901. +   /* OTP */
  902. +   uint32  otpstatus;      /* 0x10, corerev >= 10 */
  903. +   uint32  otpcontrol;
  904. +   uint32  otpprog;
  905. +   uint32  PAD1;
  906. +
  907. +   /* Interrupt control */
  908. +   uint32  intstatus;      /* 0x20 */
  909. +   uint32  intmask;
  910. +   uint32  chipcontrol;        /* 0x28, rev >= 11 */
  911. +   uint32  chipstatus;     /* 0x2c, rev >= 11 */
  912. +
  913. +   /* Jtag Master */
  914. +   uint32  jtagcmd;        /* 0x30, rev >= 10 */
  915. +   uint32  jtagir;
  916. +   uint32  jtagdr;
  917. +   uint32  jtagctrl;
  918. +
  919. +   /* serial flash interface registers */
  920. +   uint32  flashcontrol;       /* 0x40 */
  921. +   uint32  flashaddress;
  922. +   uint32  flashdata;
  923. +   uint32  PAD2[1];
  924. +
  925. +   /* Silicon backplane configuration broadcast control */
  926. +   uint32  broadcastaddress;   /* 0x50 */
  927. +   uint32  broadcastdata;
  928. +
  929. +   /* gpio - cleared only by power-on-reset */
  930. +   uint32  gpiopullup;     /* 0x58, corerev >= 20 */
  931. +   uint32  gpiopulldown;       /* 0x5c, corerev >= 20 */
  932. +   uint32  gpioin;         /* 0x60 */
  933. +   uint32  gpioout;
  934. +   uint32  gpioouten;
  935. +   uint32  gpiocontrol;
  936. +   uint32  gpiointpolarity;
  937. +   uint32  gpiointmask;
  938. +
  939. +   /* GPIO events corerev >= 11 */
  940. +   uint32  gpioevent;
  941. +   uint32  gpioeventintmask;
  942. +
  943. +   /* Watchdog timer */
  944. +   uint32  watchdog;       /* 0x80 */
  945. +
  946. +   /* GPIO events corerev >= 11 */
  947. +   uint32  gpioeventintpolarity;
  948. +
  949. +   /* GPIO based LED powersave registers corerev >= 16 */
  950. +   uint32  gpiotimerval;       /* 0x88 */
  951. +   uint32  gpiotimeroutmask;
  952. +
  953. +   /* clock control */
  954. +   uint32  clockcontrol_n;     /* 0x90 */
  955. +   uint32  clockcontrol_sb;    /* aka m0 */
  956. +   uint32  clockcontrol_pci;   /* aka m1 */
  957. +   uint32  clockcontrol_m2;    /* mii/uart/mipsref */
  958. +   uint32  clockcontrol_m3;    /* cpu */
  959. +   uint32  clkdiv;         /* corerev >= 3 */
  960. +   uint32  PAD3[2];
  961. +
  962. +   /* pll delay registers (corerev >= 4) */
  963. +   uint32  pll_on_delay;       /* 0xb0 */
  964. +   uint32  fref_sel_delay;
  965. +   uint32  slow_clk_ctl;       /* 5 < corerev < 10 */
  966. +   uint32  PAD4[1];
  967. +
  968. +   /* Instaclock registers (corerev >= 10) */
  969. +   uint32  system_clk_ctl;     /* 0xc0 */
  970. +   uint32  clkstatestretch;
  971. +   uint32  PAD5[13];
  972. +
  973. +   /* In AI chips, pointer to erom */
  974. +   uint32  eromptr;
  975. +} chipcregs_t;
  976. +
  977. +#define ER_VALID 1
  978. +#define ER_END 0xe
  979. +
  980. +static uint32
  981. +get_erom_ent(struct ssb_bus *bus, uint32 *eromptr, uint32 mask, uint32 match)
  982. +{
  983. +   uint32 ent;
  984. +   uint inv = 0, nom = 0;
  985. +
  986. +   while (1) {
  987. +       ent = readl(*eromptr);
  988. +       *eromptr += sizeof(uint32);
  989. +
  990. +       if (mask == 0)
  991. +           break;
  992. +
  993. +       if ((ent & ER_VALID) == 0) {
  994. +           inv++;
  995. +           continue;
  996. +       }
  997. +
  998. +       if (ent == (ER_END | ER_VALID))
  999. +           break;
  1000. +
  1001. +       if ((ent & mask) == match)
  1002. +           break;
  1003. +
  1004. +       nom++;
  1005. +   }
  1006. +
  1007. +   /*SI_VMSG(("%s: Returning ent 0x%08x\n", __FUNCTION__, ent));
  1008. +   if (inv + nom) {
  1009. +       SI_VMSG(("  after %d invalid and %d non-matching entries\n", inv, nom));
  1010. +   }*/
  1011. +   return ent;
  1012. +}
  1013. +#define       ER_ADD                  4
  1014. +#define       ER_TAG1                 0x6
  1015. +#define       AD_SP_MASK              0x00000f00
  1016. +#define       AD_SP_SHIFT             8
  1017. +#define       AD_ST_MASK              0x000000c0
  1018. +#define       AD_ADDR_MASK            0xfffff000
  1019. +#define       AD_AG32                 0x0000000
  1020. +#define       AD_SZ_MASK              0x00000030
  1021. +#define       AD_SZ_SZD               0x00000030
  1022. +#define       SD_SZ_MASK              0xfffff000
  1023. +#define       SD_SG32                 0x00000008
  1024. +#define       AD_SZ_SHIFT             4
  1025. +#define       AD_SZ_BASE              0x00001000
  1026. +static uint32
  1027. +get_asd(struct ssb_bus *bus, uint32 *eromptr, uint sp, uint ad, uint st, uint32 *addrl, uint32 *addrh,
  1028. +        uint32 *sizel, uint32 *sizeh)
  1029. +{
  1030. +   uint32 asd, sz, szd;
  1031. +
  1032. +   asd = get_erom_ent(bus, eromptr, ER_VALID, ER_VALID);
  1033. +   if (((asd & ER_TAG1) != ER_ADD) ||
  1034. +       (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
  1035. +       ((asd & AD_ST_MASK) != st)) {
  1036. +       /* This is not what we want, "push" it back */
  1037. +       *eromptr -= sizeof(uint32);
  1038. +       return 0;
  1039. +   }
  1040. +   *addrl = asd & AD_ADDR_MASK;
  1041. +   if (asd & AD_AG32)
  1042. +       *addrh = get_erom_ent(bus, eromptr, 0, 0);
  1043. +   else
  1044. +       *addrh = 0;
  1045. +   *sizeh = 0;
  1046. +   sz = asd & AD_SZ_MASK;
  1047. +   if (sz == AD_SZ_SZD) {
  1048. +       szd = get_erom_ent(bus, eromptr, 0, 0);
  1049. +       *sizel = szd & SD_SZ_MASK;
  1050. +       if (szd & SD_SG32)
  1051. +           *sizeh = get_erom_ent(bus, eromptr, 0, 0);
  1052. +   } else
  1053. +       *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
  1054. +
  1055. +   printk("  SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
  1056. +           sp, ad, st, *sizeh, *sizel, *addrh, *addrl);
  1057. +
  1058. +   return asd;
  1059. +}
  1060. +
  1061. +int ssb_bus_scan(struct ssb_bus *bus,
  1062. +        unsigned long baseaddr)
  1063. +{
  1064. +   chipcregs_t *cc = (chipcregs_t *)baseaddr;
  1065. +   uint32 erombase, eromptr, eromlim;
  1066. +
  1067. +   erombase = readl(KSEG1ADDR(&cc->eromptr));
  1068. +#define SI_CORE_SIZE         0x1000
  1069. +#define       ER_TAG                  0xe
  1070. +#define       ER_CI                   0
  1071. +
  1072. +   eromptr = (u32)ioremap(erombase, SI_CORE_SIZE);
  1073. +
  1074. +   eromlim = eromptr + SI_CORE_SIZE;
  1075. +  
  1076. +   bus->nr_devices = 0;
  1077. +
  1078. +   printk("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%08x, eromlim = 0x%08x\n",
  1079. +            baseaddr, erombase, eromptr, eromlim);
  1080. +   while (eromptr < eromlim) {
  1081. +       uint32 cia, cib, base, cid, mfg, crev, nmw, nsw, nmp, nsp;
  1082. +       uint32 mpd, asd, addrl, addrh, sizel, sizeh;
  1083. +       uint i, j, idx;
  1084. +       bool br;
  1085. +       struct ssb_device *dev = &(bus->devices[bus->nr_devices]);
  1086. +       br = 0;
  1087. +
  1088. +       /* Grok a component */
  1089. +       cia = get_erom_ent(bus, &eromptr, ER_TAG, ER_CI);
  1090. +       if (cia == (ER_END | ER_VALID)) {
  1091. +           printk("Found END of erom after %d cores\n", bus->nr_devices);
  1092. +           return 0;
  1093. +       }
  1094. +       base = eromptr - sizeof(uint32);
  1095. +       cib = get_erom_ent(bus, &eromptr, 0, 0);
  1096. +#define       CIA_CID_MASK            0x000fff00
  1097. +#define       CIA_CID_SHIFT           8
  1098. +#define       CIA_MFG_MASK            0xfff00000
  1099. +#define       CIA_MFG_SHIFT           20
  1100. +#define       CIB_REV_MASK            0xff000000
  1101. +#define       CIB_REV_SHIFT           24
  1102. +#define       CIB_NMW_MASK            0x0007c000
  1103. +#define       CIB_NMW_SHIFT           14
  1104. +#define       CIB_NSW_SHIFT           19
  1105. +#define       CIB_NSW_MASK            0x00f80000
  1106. +#define       CIB_NMP_MASK            0x000001f0
  1107. +#define       CIB_NMP_SHIFT           4
  1108. +#define       CIB_NSP_SHIFT           9
  1109. +#define       CIB_NSP_MASK            0x00003e00
  1110. +#define       MFGID_ARM               0x43b
  1111. +#define      DEF_AI_COMP             0xfff
  1112. +#define       ER_MP                   2
  1113. +#define       MPD_MP_MASK             0x000000f0
  1114. +#define       MPD_MP_SHIFT            4
  1115. +#define       MPD_MUI_MASK            0x0000ff00
  1116. +#define       MPD_MUI_SHIFT           8
  1117. +#define       AD_ST_SLAVE             0x00000000
  1118. +#define       AD_ST_BRIDGE            0x00000040
  1119. +
  1120. +       if ((cib & ER_TAG) != ER_CI) {
  1121. +           printk("CIA not followed by CIB\n");
  1122. +           goto error;
  1123. +       }
  1124. +
  1125. +       cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
  1126. +       mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
  1127. +       crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
  1128. +       nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
  1129. +       nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
  1130. +       nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
  1131. +       nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
  1132. +
  1133. +       dev->id.coreid = cid;
  1134. +       dev->id.revision = crev;
  1135. +       dev->id.vendor = mfg;
  1136. +       dev->core_index = bus->nr_devices;
  1137. +       dev->bus = bus;
  1138. +       dev->ops = bus->ops;
  1139. +
  1140. +       ssb_printk(KERN_INFO PFX
  1141. +               "Core %d found: %s "
  1142. +               "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
  1143. +               bus->nr_devices, ssb_core_name(dev->id.coreid),
  1144. +               dev->id.coreid, dev->id.revision, dev->id.vendor);
  1145. +
  1146. +       printk("Found component 0x%04x/0x%04x rev %d at erom addr 0x%08x, with nmw = %d, "
  1147. +                "nsw = %d, nmp = %d & nsp = %d\n",
  1148. +                mfg, cid, crev, base, nmw, nsw, nmp, nsp);
  1149. +
  1150. +       if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) ||
  1151. +           (nmw + nsw == 0) || (nsp == 0)) {
  1152. +           printk("A component which is not a core\n");
  1153. +           continue;
  1154. +       }
  1155. +
  1156. +
  1157. +       for (i = 0; i < nmp; i++) {
  1158. +           mpd = get_erom_ent(bus, &eromptr, ER_VALID, ER_VALID);
  1159. +           if ((mpd & ER_TAG) != ER_MP) {
  1160. +               printk("Not enough MP entries for component 0x%x\n", cid);
  1161. +               goto error;
  1162. +           }
  1163. +           printk("  Master port %d, mp: %d id: %d\n", i,
  1164. +                    (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
  1165. +                    (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT);
  1166. +       }
  1167. +#define       AD_ST_MWRAP             0x000000c0
  1168. +#define       AD_ST_SWRAP             0x00000080
  1169. +       /* First Slave Address Descriptor should be port 0:
  1170. +        * the main register space for the core
  1171. +        */
  1172. +       asd = get_asd(bus, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
  1173. +       if (asd == 0) {
  1174. +           /* Try again to see if it is a bridge */
  1175. +           asd = get_asd(bus, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
  1176. +                         &sizel, &sizeh);
  1177. +           if (asd != 0)
  1178. +               br = true;
  1179. +           else
  1180. +               if ((addrh != 0) || (sizeh != 0) || (sizel != SI_CORE_SIZE)) {
  1181. +                   printk("First Slave ASD for core 0x%04x malformed "
  1182. +                             "(0x%08x)\n", cid, asd);
  1183. +                   goto error;
  1184. +               }
  1185. +       }
  1186. +       /* Get any more ASDs in port 0 */
  1187. +       j = 1;
  1188. +       do {
  1189. +           asd = get_asd(bus, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
  1190. +                         &sizel, &sizeh);
  1191. +           if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE))
  1192. +           j++;
  1193. +       } while (asd != 0);
  1194. +
  1195. +       /* Go through the ASDs for other slave ports */
  1196. +       for (i = 1; i < nsp; i++) {
  1197. +           j = 0;
  1198. +           do {
  1199. +               asd = get_asd(bus, &eromptr, i, j++, AD_ST_SLAVE, &addrl, &addrh,
  1200. +                             &sizel, &sizeh);
  1201. +           } while (asd != 0);
  1202. +           if (j == 0) {
  1203. +               printk(" SP %d has no address descriptors\n", i);
  1204. +               goto error;
  1205. +           }
  1206. +       }
  1207. +
  1208. +       /* Now get master wrappers */
  1209. +       for (i = 0; i < nmw; i++) {
  1210. +           asd = get_asd(bus, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
  1211. +                         &sizel, &sizeh);
  1212. +           if (asd == 0) {
  1213. +               printk("Missing descriptor for MW %d\n", i);
  1214. +               goto error;
  1215. +           }
  1216. +           if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
  1217. +               printk("Master wrapper %d is not 4KB\n", i);
  1218. +               goto error;
  1219. +           }
  1220. +       }
  1221. +
  1222. +       /* And finally slave wrappers */
  1223. +       for (i = 0; i < nsw; i++) {
  1224. +           uint fwp = (nsp == 1) ? 0 : 1;
  1225. +           asd = get_asd(bus, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
  1226. +                         &sizel, &sizeh);
  1227. +           if (asd == 0) {
  1228. +               printk("Missing descriptor for SW %d\n", i);
  1229. +               goto error;
  1230. +           }
  1231. +           if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
  1232. +               printk("Slave wrapper %d is not 4KB\n", i);
  1233. +               goto error;
  1234. +           }
  1235. +       }
  1236. +
  1237. +       /* Don't record bridges */
  1238. +       if (br)
  1239. +           continue;
  1240. +
  1241. +       /* Done with core */
  1242. +       bus->nr_devices++;
  1243. +   }
  1244. +
  1245. +   printk("Reached end of erom without finding END");
  1246. +
  1247. +error:
  1248. +   bus->nr_devices = 0;
  1249. +   return -1;
  1250. +}
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