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AfeefAhmed

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Jan 7th, 2021
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  1. --Afeef Ahmed jarif
  2. --180041241
  3. library IEEE;
  4. use IEEE.STD_LOGIC_1164.ALL;
  5.  
  6.  
  7. entity comparator is
  8. port (
  9.       clock: in std_logic;
  10.      
  11.       A,B: in std_logic_vector(7 downto 0);
  12.      
  13.       IAB: in std_logic; -- Expansion input ( Active low)
  14.       Output: out std_logic -- Output = 0 when A = B
  15.  );
  16. end comparator;
  17. architecture Behavioral of comparator is
  18. signal AB: std_logic_vector(7 downto 0);
  19. signal Result: std_logic;
  20. begin
  21.  
  22.  AB(0) <= (not A(0)) xnor (not B(0));        
  23.         -- combinational circuit
  24.  AB(1) <= (not A(1)) xnor (not B(1));
  25.  AB(2) <= (not A(2)) xnor (not B(2));
  26.  AB(3) <= (not A(3)) xnor (not B(3));
  27.  AB(4) <= (not A(4)) xnor (not B(4));
  28.  AB(5) <= (not A(5)) xnor (not B(5));
  29.  AB(6) <= (not A(6)) xnor (not B(6));
  30.  AB(7) <= (not A(7)) xnor (not B(7));
  31.  
  32.  process(clock)
  33.  begin
  34.  if(rising_edge(clock))then
  35.    if(AB = x"FF" and IAB = '0') then        
  36.          
  37.             Result <= '0';
  38.     else
  39.      Result <= '1';
  40.     end if;
  41.  end if;
  42.  end process;
  43.  Output <= Result;
  44. end Behavioral;
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