LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity ADDC1 is
    port (A, B, CIN: in std_logic;
    SUM, COUT: out std_logic);
end ADDC1;

architecture DESCRIPTION of ADDC1 is
begin
    SUM <= (A xor B xor CIN);
    COUT <= ((A and B) or (B and CIN) or (A and CIN));
end DESCRIPTION;