library ieee;
use ieee.std_logic_1164.all;

package A_PKG is

    type tA is array (0 to 2**8-1) of std_logic_vector(32-1 downto 0);

end package A_PKG;

package body A_PKG is

end package body A_PKG;

library ieee;
use ieee.std_logic_1164.all;
use work.A_PKG.all;

entity E is
    port (
        iCLK : in  std_logic;
        iCLR : in  std_logic;
        iA   : in  tA;
        oA   : out tA
    );
begin
end entity E;

architecture RTL of E is

    constant cA : tA := (0 to 2**8-1 => (32-1 downto 0 => '0'));
    signal   rA : tA := cA;

begin

    P_rA : process (iCLK)
    begin
        if (rising_edge(iCLK)) then
            if (iCLR = '1') then
                rA <= cA;
            else
                rA <= iA;
            end if;
        end if;
    end process P_rA;

    oA <= rA;

end architecture RTL;

library ieee;
use ieee.std_logic_1164.all;
use work.A_PKG.all;

entity E2E is
    port (
        iCLK : in  std_logic;
        iCLR : in  std_logic;
        iA   : in  tA;
        oA   : out tA
    );
begin
end entity E2E;

architecture STRUCTURE of E2E is

    component E is
        port (
            iCLK : in  std_logic;
            iCLR : in  std_logic;
            iA   : in  tA;
            oA   : out tA
        );
    end component E;
    for all : E use entity work.E(RTL);

    signal sE1_oA : tA;

begin

    U_E1 : E
    port map (
        iCLK => iCLK,
        iCLR => iCLR,
        iA   => iA,
        oA   => sE1_oA
    );

    U_E2 : E
    port map (
        iCLK => iCLK,
        iCLR => iCLR,
        iA   => sE1_oA,
        oA   => oA
    );

end architecture STRUCTURE;

-- RTL_SYNTHESIS OFF
library ieee;
use ieee.std_logic_1164.all;
use work.A_PKG.all;

entity BENCH_E2E is
begin
end entity BENCH_E2E;

architecture BENCH of BENCH_E2E is

    constant cCLK_PERIOD : time := 1.0 ns;
    constant cCLR_TIME   : time := 3*cCLK_PERIOD;

    signal sCLK  : std_logic := '0';
    signal sCLR  : std_logic := '1';
    signal rDONE : std_logic := '0';

    component E2E is
        port (
            iCLK : in  std_logic;
            iCLR : in  std_logic;
            iA   : in  tA;
            oA   : out tA
        );
    end component E2E;
    for all : E2E use entity work.E2E(STRUCTURE);

    signal rE2E_iA : tA := (0 to 2**8-1 => (32-1 downto 0 => '0'));
    signal sE2E_oA : tA;

begin

    P_sCLK : process
    begin
        W_sCLK : while (rDONE /= '1') loop
            sCLK <= '0'; wait for cCLK_PERIOD/2;
            sCLK <= '1'; wait for cCLK_PERIOD/2;
        end loop W_sCLK;
        wait;
    end process P_sCLK;

    P_sCLR : process
    begin
        sCLR <= '1'; wait for cCLR_TIME;
        sCLR <= '0'; wait;
    end process P_sCLR;

    P_STIM : process
    begin
        wait until (sCLR /= '1');
        wait until (rising_edge(sCLK));

        F_STIM_i : for i in 0 to 2**8-1 loop
            F_STIM_j : for j in 32-1 downto 0 loop
                rE2E_iA(i)(j) <= '1';
                wait until (rising_edge(sCLK));
            end loop F_STIM_j;
        end loop F_STIM_i;

        wait for 2*cCLK_PERIOD; -- NOTE: I/O latency of E2E.
        wait until (rising_edge(sCLK));

        rDONE <= '1';
        wait;
    end process P_STIM;

    U_E2E : E2E
    port map (
        iCLK => sCLK,
        iCLR => sCLR,
        iA   => rE2E_iA,
        oA   => sE2E_oA
    );

end architecture BENCH;
-- RTL_SYNTHESIS ON