module main #(parameter WL1 = 32, WL2 = 32, WL = 32, WLinput = 5, WLcon = 6, WLsign = 16, WLalu = 4)
(
 output signed [WL-1:0] ALUout,
 output [WL-1:0] result
    );
wire clk;
wire rst;
wire [((WL1 > WL2 ? WL1+1:WL2+1)-1):0] PCp1;
wire [WL-1:0] PCbefore;
wire [WL-1:0] PCBranch;
wire PCsel;
wire [WL-1:0] PCjump;
wire [WL-1:0] PC;

wire [WLcon-1:0] opco,funct;
wire zero, jump, RDsel, ALUnSel, branch, MWE, MRFSel; //control signal values from control unit
wire [1:0] ALUop; //alu opcode from control unit
wire RFWE;
wire [3:0] ALUsel;
wire [WL-1:0] ALUIn2;
wire [WLalu:0] shamt;

wire [WL-1:0] D1,D2; //read data ports from register file, and write data from register file
//address ports for output
wire [WLinput-1:0] rs;
wire [WLinput-1:0] rd;
wire [WLinput-1:0] rt; //write address port from register file
wire [WLinput-1:0] rtd;
wire [WL-1:0] Jaddr;

//wire [WLinput-1:0] IMA; //5 bit input of address from instruction memory
wire [WL-1:0] inst; //output 32 bit instruction from instruction memory

wire [WL-1:0] Simm;
wire [WLsign-1:0] Imm; //variables for sign extension module

wire signed [WL-1:0] DMout;
wire signed [WL-1:0] ALUDM;

clk c1(.clk(clk), .rst(rst)); //calling clock to start first rising edge

//mux #(.WL(WL)) mux0(
PC #(.WL(WL)) p1(.clk(clk), .PC_input(PC), .PC_result(result)); //instantiating PC to 0

adder #(.WL1(WL1), .WL2(WL2), .WL0((WL1 > WL2 ? WL1+1:WL2+1))) a1(.x(result), .y(1), .out(PCp1));
 //pc is incremented by adder and the new address is written into th epC on the next rising edge of clk

instruction #(.WLinput(WLinput), .WL(WL)) in1(.IMA(result), .instruction(inst));
//instruction memory takes in textfile with program counter giving the address point

assign opco = inst[31:26];
assign funct = inst[5:0];
control #(.WLcon(WLcon)) con1(.rst(rst), .opcode(opco), .RFWE(RFWE),.RFDsel(RDsel), .ALUInSel(ALUnSel), .Branch(branch), .DMWE(MWE), .MtoRFSel(MRFSel), .ALUop(ALUop), .ALUsel(ALUsel), .Jump(jump), .funct(funct));


assign rs = inst[25:21]; //rs
assign rt = inst[20:16];
assign rd = inst[15:11];
assign shamt = inst[10:6];
assign Jaddr = inst[25:0];
//RF_module #(.WL(WL), .WLinput(WLinput)) rf1(.RFRD1(D1), .RFRD2(D2), .RFRA1(rs), .RFRA2(rt), .WA(WA), .WD(WD), .rst(rst), .clk(clk), .WE(RFWE));
//calling register file with instruction memory 5 bit read address, and write enable from control unit

assign Imm = inst[15:0];
SIMM #(.WLsign(WLsign), .WL(WL)) sim1(.unextended(Imm), .extended(Simm));
//sign extends the 16 bit immediate and puts into Simm

RF_module #(.WL(WL), .WLinput(WLinput)) rf1(.RFRD1(D1), .RFRD2(D2), .RFRA1(rs), .RFRA2(rt), .WA(rtd), .WD(ALUDM), .clk(clk), .rst(rst), .WE(RFWE));

adder #(.WL1(WL1), .WL2(WL2), .WL0((WL1 > WL2 ? WL1+1:WL2+1))) a2(.x(Simm), .y(PCp1), .out(PCBranch));

mux #(.WL(WL)) mux1(.in1(D2), .in2(Simm), .sel(ALUnSel), .out(ALUIn2));

ALU_module #(.WL(WL), .WLalu(WLalu)) alu1(.ALU_in1(D1), .ALU_in2(ALUIn2), .ALU_sel(ALUsel), .ALU_out(ALUout), .zero_or_nah(zero), .shamt(shamt));
//alu generates a 32 bit ALUout and a ZERO FLAG THAT INDICATES WHERE ALUOUT == 0
assign PCjump = {PCp1[31:26], Jaddr};
assign PCsel = branch & zero;
mux #(.WL(WL)) mux3(.in1(PCp1), .in2(PCBranch), .sel(PCsel), .out(PCbefore));
mux #(.WL(WL)) mux5(.in1(PCbefore), .in2(PCjump), .sel(jump), .out(PC));

data #(.WL(WL), .WLinput(WLinput)) data1(.DMWD(D2), .DMWE(MWE), .clk(clk), .DMA(ALUout), .DMRD(DMout));
//data is read from data memory onto DMRD ports then written back to destination register specified by rt

mux #(.WL(WL)) mux2(.in1(rt), .in2(rd), .sel(RDsel), .out(rtd));
mux #(.WL(WL)) mux4(.in1(ALUout), .in2(DMout), .sel(MRFSel), .out(ALUDM));
//load word
//RF_module #(.WL(WL), .WLinput(WLinput)) rf2(.RFRD1(D1), .RFRD2(D2), .RFRA1(rs), .RFRA2(rt), .WA(rtd), .WD(ALUDM), .clk(clk), .rst(rst), .WE(RFWE));

endmodule