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  1. module swb2(SW, KEY, LEDR, HEX0, HEX1, HEX2, HEX3);
  2. input [9:0] SW;
  3. input [3:0] KEY;
  4. output reg [9:0] LEDR;
  5. output [6:0] HEX0;
  6. output [6:0] HEX1;
  7. output [6:0] HEX2;
  8. output reg [6:0] HEX3;
  9.  
  10. always
  11. begin
  12.     if (KEY[0]==0)
  13.         LEDR[9:0]=SW[9:5]+SW[4:0];
  14.     else
  15.        
  16.        
  17.     if (KEY[1]==0)
  18.         if(SW[9:5] >= SW[4:0])
  19.             LEDR[9:0]=SW[9:5]-SW[4:0];
  20.         else
  21.             LEDR[9:0]=SW[4:0]-SW[9:5];
  22.     else
  23.        
  24.        
  25.     if (KEY[2]==0)
  26.         LEDR[9:0]=SW[9:5]*SW[4:0];
  27.     else
  28.         LEDR[9:0]=SW[9:0];
  29. end
  30.  
  31. dec_to_hex y(LEDR % 10, HEX0);
  32. dec_to_hex e((LEDR/10) % 10, HEX1);
  33. dec_to_hex r(((LEDR/10)/10) % 10, HEX2);
  34. always
  35.     if (SW[9:5] < SW[4:0])
  36.         HEX3 = 7'b0111111;
  37.     else
  38.         HEX3 = 7'b1111111;
  39.  
  40.  
  41. endmodule
  42.  
  43. module dec_to_hex(digit, bits);
  44. input [3:0] digit;
  45. output reg [6:0] bits;
  46.  
  47. always
  48. case (digit)
  49.     0: bits = 7'b1000000;
  50.     1: bits = 7'b1111001;
  51.     2: bits = 7'b0100100;
  52.     3: bits = 7'b0110000;
  53.     4: bits = 7'b0011001;
  54.     5: bits = 7'b0010010;
  55.     6: bits = 7'b0000010;
  56.     7: bits = 7'b1111000;
  57.     8: bits = 7'b0000000;
  58.     9: bits = 7'b0010000;
  59.     default: bits = 7'b1111111;
  60. endcase
  61.  
  62. endmodule
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