Date: Thu, 19 Sep 2019 11:59:53 +0000 (UTC)
From: NLnet submission system <webmaster@nlnet.nl>
To: projects@nlnet.nl, webmaster@nlnet.nl
Subject: [NLnet NREN] andreas.westerwick@libresilicon.com
Reply-To: andreas.westerwick@libresilicon.com


The following support request was made via NLnet's website:

  Code        : 2019-10-023
  Requestor   : Andreas Westerwick
  Email       : andreas.westerwick@libresilicon.com
  Phone       : +852 5625 0211
  Organization: LibreSilicon
  Country     : Hong Kong
  Consent     : You may keep my data on record
  Call        : NREN
  Project     : Libre Silicon compiler
  Website     : https://libresilicon.com
  Abstract    : The Libre Silicon compiler (lsc) is an open source
                project to synthesize, place and route hardware
                description to silicon.
                Hardware description is usually done in Verilog or even
                higher languages such as Chisel. The goal of this
                project is to provide a command-line tool that will
                solve several NP-hard problems related to hardware
                design.
                The compiler software is provided with process-specific
                libraries and design constraints and a module to
                synthesize to silicon. To do this, the module given in
                RTL (e. g. verilog) is broken up into primitive
                standard cells (flip-flops, pure logic gates, buffers).
                This process is called synthesis.
                After synthesis the problem arises from arranging the
                standard cells on the silicon wafer in a way that the
                chip works efficiently (e.g. clock rate, chip area).
                This process is called placement.
                When all cells are arranged geographically, another
                problem arises from connecting them through wires in a
                way that minimizes clock rate, while not violating
                design constraints.
                This process is called routing.
                After this is all done, the result can easily be output
                to established file formats for fabrication (e.g.
                GDSII).
  Experience  : I'm part of the LibreSilicon project. Usually I support
                the team in software related problems.
                I have started the Libre Silicon compiler project:
                https://redmine.libresilicon.com/projects/lsc
  Amount      : 50000
  Use         : This covers the cost for 18 months FTE to work on the
                compiler software and related software projects.
  Comparison  : Numerous open source for synthesizing, place and route
                exist. They are highly specialized in the FPGA
                technology as opposed to silicon. This is due to the
                fact that there is no open source silicon process, yet.
                Existing toolsets are highly compartmentalized and
                interface through legacy file formats. This problem is
                widely recognized in the maker scene and lsc tries to
                solve to solve this.
  Challenges  : Applying existing research in Place + Route to code.
                Often times, the publicly available research is
                fragmentary or outdated. This calls for creative
                solutions and research on our side, while building on
                top of existing knowledge.
  Ecosystem   : The project will be available on our redmine. As is the
                nature of open source projects, we expect several forks
                of this software to be available on github. The GPL
                license requires contributions to the software to be
                published.
                Both github and redmine offer a platform to raise
                issues that arise from usage in production.