module count(
  input wire reset,
  input wire clk,
  output reg [5:0]counter
);
always @(posedge clk or posedge reset)
  if(reset)
    counter <= 6'd0;
  else
    counter <= counter + 1'd1;
endmodule


module decoder(
  input wire [2:0]in,
  output reg [7:0]out
);

always @*
begin
  case(in)
   3'd0: out=8'b00000001;
   3'd1: out=8'b00000010;
   3'd2: out=8'b00000100;
   3'd3: out=8'b00001000;
   3'd4: out=8'b00010000;
   3'd5: out=8'b00100000;
   3'd6: out=8'b01000000;
   3'd7: out=8'b10000000;
  endcase
end
endmodule

module selector(
  input wire [5:0]sig,
  input wire [7:0]sel,
  input wire sig1,
  output reg out;
);

always @*
begin
case(sel)        // 2 4 8  F
   3'd0: out=sig1;   // 0 0 0  1
   3'd1: out=sig[0]; // 1 0 0  2
   3'd2: out=sig[1]; // 0 1 0  4
   3'd3: out=sig[2]; // 1 1 0  8
   3'd4: out=sig[2]; // 0 0 1  8
   3'd5: out=sig[3]; // 1 0 1  16
   3'd6: out=sig[4]; // 0 1 1  32
   3'd7: out=sig[5]; // 1 1 1  64
  endcase
end
endmodule

module task(
  input wire [2:0]selector,
  input wire clk,
  input wire reset,
  output wire signal
);
wire [5:0]c,
wire [7:0]d;

always @(posedge clk or posedge reset)
begin
   count(.clk (clk) , .reset (reset), .counter (c));
   decoder(.in (selector), .out (d));
   selector(.sig (c), .sel (d), .sig1 (clk), .out(signal));
end
endmodule