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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. use ieee.std_logic_unsigned.ALL;
  5. use ieee.std_logic_arith.all;
  6. library ieee;
  7. use ieee.std_logic_1164.all;
  8. entity half_adder is
  9.     port(i_1 : in STD_LOGIC;
  10.      i_2 : in STD_LOGIC;
  11.      o_sum : out STD_LOGIC;
  12.      o_carry : out STD_LOGIC);
  13. end half_adder;
  14. architecture DATAFLOW of half_adder is
  15. begin
  16. o_carry<=i_1 and i_2;
  17. o_sum<=i_1 xor i_2;    
  18. end DATAFLOW;
  19. library ieee;
  20. use ieee.std_logic_1164.all;
  21. entity full_adder is
  22.     port( i_carry: in STD_LOGIC;
  23.       i_1 : in STD_LOGIC;
  24.       i_2 : in STD_LOGIC;
  25.       o_sum : out STD_LOGIC;
  26.       o_carry : out STD_LOGIC);
  27. end full_adder;
  28.  
  29. architecture STRUCTURAL of full_adder is
  30. component half_adder is
  31.     port(a : in STD_LOGIC;
  32.      b : in STD_LOGIC;
  33.      s : out STD_LOGIC;
  34.      c : out STD_LOGIC);
  35. end component;
  36. signal t1,t2,t3:  STD_LOGIC;
  37. begin
  38. m1: half_adder port map(a=>i_1,b=>i_2,s=>t1,c=>t2);
  39. m2: half_adder port map(a=>t1,b=>i_carry,s=>o_sum,c=>t3);
  40. o_carry<= t2 or t3;
  41. end STRUCTURAL;
  42. library ieee;
  43. use ieee.std_logic_1164.all;
  44.  
  45. entity ripple_adder is
  46.     port( input_1 : in STD_LOGIC_VECTOR(3 downto 0);
  47.           input_2 : in STD_LOGIC_VECTOR(3 downto 0);
  48.       o_sum : out STD_LOGIC_VECTOR(3 downto 0);
  49.       o_carry : out STD_LOGIC);
  50. end ripple_adder;
  51. architecture STRUCTURAL of ripple_adder is
  52. component full_adder is
  53.     port( i_carry: in STD_LOGIC;
  54.       i_1 : in STD_LOGIC;
  55.       i_2 : in STD_LOGIC;
  56.       o_sum : out STD_LOGIC;
  57.       c : out STD_LOGIC);
  58. end component;
  59. signal t1,t2,t3,t4:  STD_LOGIC;
  60.  
  61. begin
  62. m1: full_adder port map(i_1=>input_1(0),i_2=>input_2(0),i_carry=>'0',o_sum=>o_sum(0),c=>t1);
  63. m2: full_adder port map(i_1=>input_1(1),i_2=>input_2(1),i_carry=>t1,o_sum=>o_sum(1),c=>t2);
  64. m3: full_adder port map(i_1=>input_1(2),i_2=>input_1(2),i_carry=>t2,o_sum=>o_sum(2),c=>t3);
  65. m4: full_adder port map(i_1=>input_1(3),i_2=>input_1(3),i_carry=>t3,o_sum=>o_sum(3),c=>t4);
  66. o_carry<=t4;
  67.  
  68. end STRUCTURAL;
  69.  
  70.  
  71. entity lab_tb is
  72. end lab_tb;
  73. library ieee;
  74. use ieee.std_logic_1164.all;
  75. library ieee;
  76. use ieee.std_logic_1164.all;
  77. use ieee.numeric_std.all;
  78. use ieee.std_logic_unsigned.ALL;
  79. use ieee.std_logic_arith.all;
  80. architecture TESTBENCH of lab_tb is
  81. signal input_1: STD_LOGIC_VECTOR(3 downto 0):="0000";
  82. signal input_2: STD_LOGIC_VECTOR(3 downto 0):="0000";
  83. signal sum: STD_LOGIC_VECTOR(3 downto 0):="0000";
  84. signal carry: STD_LOGIC:='0';
  85. signal validate: STD_LOGIC_VECTOR(4 downto 0):="00000";
  86. signal asserted: STD_LOGIC :='0';
  87. component ripple_adder is
  88.     port( input_1 : in STD_LOGIC_VECTOR(3 downto 0);
  89.           input_2 : in STD_LOGIC_VECTOR(3 downto 0);
  90.       o_sum : out STD_LOGIC_VECTOR(3 downto 0);
  91.       o_carry : out STD_LOGIC);
  92. end component;    
  93. begin  
  94. ADDER_MAP: ripple_adder port map( input_1=>input_1, input_2=>input_2,o_sum=>sum,o_carry=>carry);
  95. validate(3 downto 0) <= conv_std_logic_vector
  96.     (to_integer(ieee.numeric_std.unsigned(input_1))
  97.         + to_integer(ieee.numeric_std.unsigned(input_2)), sum'length) xor sum;
  98. validate(4) <= carry  when
  99.     (to_integer(ieee.numeric_std.unsigned(input_1))
  100.         + to_integer(ieee.numeric_std.unsigned(input_2)) < 16)
  101.             else (not carry);
  102. asserted <= '0' when validate=0 else '1' ;
  103. process
  104.     begin
  105.     --trivial input    
  106.     input_1<="0010";
  107.     input_2<="0101";
  108.     wait for 10 ns;
  109.     -- a+b = b+a
  110.     input_1<="0101";
  111.     input_2<="0010";
  112.     wait for 10 ns;
  113.     --zero input   
  114.     input_1<="0000";
  115.     input_2<="0000";
  116.     wait for 10 ns;
  117.     --1 step carry 
  118.     input_1<="0001";
  119.     input_2<="0001";
  120.     wait for 10 ns;
  121.     --carry sum input  
  122.     input_1<="0001";
  123.     input_2<="0011";
  124.     wait for 10 ns;
  125.     --ripple carry 
  126.     input_1<="0111";
  127.     input_2<="0011";
  128.     wait for 10 ns;
  129.     --overflow 
  130.     input_1<="1111";
  131.     input_2<="0001";
  132.     wait for 10 ns;
  133.     end process;
  134. end TESTBENCH;
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