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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- use ieee.std_logic_unsigned.ALL;
- use ieee.std_logic_arith.all;
- library ieee;
- use ieee.std_logic_1164.all;
- entity half_adder is
- port(i_1 : in STD_LOGIC;
- i_2 : in STD_LOGIC;
- o_sum : out STD_LOGIC;
- o_carry : out STD_LOGIC);
- end half_adder;
- architecture DATAFLOW of half_adder is
- begin
- o_carry<=i_1 and i_2;
- o_sum<=i_1 xor i_2;
- end DATAFLOW;
- library ieee;
- use ieee.std_logic_1164.all;
- entity full_adder is
- port( i_carry: in STD_LOGIC;
- i_1 : in STD_LOGIC;
- i_2 : in STD_LOGIC;
- o_sum : out STD_LOGIC;
- o_carry : out STD_LOGIC);
- end full_adder;
- architecture STRUCTURAL of full_adder is
- component half_adder is
- port(a : in STD_LOGIC;
- b : in STD_LOGIC;
- s : out STD_LOGIC;
- c : out STD_LOGIC);
- end component;
- signal t1,t2,t3: STD_LOGIC;
- begin
- m1: half_adder port map(a=>i_1,b=>i_2,s=>t1,c=>t2);
- m2: half_adder port map(a=>t1,b=>i_carry,s=>o_sum,c=>t3);
- o_carry<= t2 or t3;
- end STRUCTURAL;
- library ieee;
- use ieee.std_logic_1164.all;
- entity ripple_adder is
- port( input_1 : in STD_LOGIC_VECTOR(3 downto 0);
- input_2 : in STD_LOGIC_VECTOR(3 downto 0);
- o_sum : out STD_LOGIC_VECTOR(3 downto 0);
- o_carry : out STD_LOGIC);
- end ripple_adder;
- architecture STRUCTURAL of ripple_adder is
- component full_adder is
- port( i_carry: in STD_LOGIC;
- i_1 : in STD_LOGIC;
- i_2 : in STD_LOGIC;
- o_sum : out STD_LOGIC;
- c : out STD_LOGIC);
- end component;
- signal t1,t2,t3,t4: STD_LOGIC;
- begin
- m1: full_adder port map(i_1=>input_1(0),i_2=>input_2(0),i_carry=>'0',o_sum=>o_sum(0),c=>t1);
- m2: full_adder port map(i_1=>input_1(1),i_2=>input_2(1),i_carry=>t1,o_sum=>o_sum(1),c=>t2);
- m3: full_adder port map(i_1=>input_1(2),i_2=>input_1(2),i_carry=>t2,o_sum=>o_sum(2),c=>t3);
- m4: full_adder port map(i_1=>input_1(3),i_2=>input_1(3),i_carry=>t3,o_sum=>o_sum(3),c=>t4);
- o_carry<=t4;
- end STRUCTURAL;
- entity lab_tb is
- end lab_tb;
- library ieee;
- use ieee.std_logic_1164.all;
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- use ieee.std_logic_unsigned.ALL;
- use ieee.std_logic_arith.all;
- architecture TESTBENCH of lab_tb is
- signal input_1: STD_LOGIC_VECTOR(3 downto 0):="0000";
- signal input_2: STD_LOGIC_VECTOR(3 downto 0):="0000";
- signal sum: STD_LOGIC_VECTOR(3 downto 0):="0000";
- signal carry: STD_LOGIC:='0';
- signal validate: STD_LOGIC_VECTOR(4 downto 0):="00000";
- signal asserted: STD_LOGIC :='0';
- component ripple_adder is
- port( input_1 : in STD_LOGIC_VECTOR(3 downto 0);
- input_2 : in STD_LOGIC_VECTOR(3 downto 0);
- o_sum : out STD_LOGIC_VECTOR(3 downto 0);
- o_carry : out STD_LOGIC);
- end component;
- begin
- ADDER_MAP: ripple_adder port map( input_1=>input_1, input_2=>input_2,o_sum=>sum,o_carry=>carry);
- validate(3 downto 0) <= conv_std_logic_vector
- (to_integer(ieee.numeric_std.unsigned(input_1))
- + to_integer(ieee.numeric_std.unsigned(input_2)), sum'length) xor sum;
- validate(4) <= carry when
- (to_integer(ieee.numeric_std.unsigned(input_1))
- + to_integer(ieee.numeric_std.unsigned(input_2)) < 16)
- else (not carry);
- asserted <= '0' when validate=0 else '1' ;
- process
- begin
- --trivial input
- input_1<="0010";
- input_2<="0101";
- wait for 10 ns;
- -- a+b = b+a
- input_1<="0101";
- input_2<="0010";
- wait for 10 ns;
- --zero input
- input_1<="0000";
- input_2<="0000";
- wait for 10 ns;
- --1 step carry
- input_1<="0001";
- input_2<="0001";
- wait for 10 ns;
- --carry sum input
- input_1<="0001";
- input_2<="0011";
- wait for 10 ns;
- --ripple carry
- input_1<="0111";
- input_2<="0011";
- wait for 10 ns;
- --overflow
- input_1<="1111";
- input_2<="0001";
- wait for 10 ns;
- end process;
- end TESTBENCH;
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