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Akalaman

Registro 4 bit, clock fronte salita

Jul 9th, 2019
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VHDL 0.44 KB | None | 0 0
  1. library IEEE;
  2. use IEEE_STD_LOGIC_1164.all;
  3. Entity MyReg is
  4. port(clk,clr: in STD_LOGIC;
  5.     D: in STD_LOGIC_VECTOR(3 downto 0);
  6.     Q: out STD_LOGIC_VECTOR(3 downto 0));
  7. end MyReg;
  8.  
  9. Architecture behavioral of MyReg is
  10. begin
  11.     process(clk, clr)
  12.     begin
  13.         if clr='1' then
  14.             Q<=(others=>'0');
  15.         else if rising_edge(clk) then \\va anche bene (clk'event and clk='1') invece di rising_edge(clk)
  16.             Q<=D;
  17.         end if;
  18.     end process;
  19. end behavioral;
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