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- library IEEE;
- use IEEE_STD_LOGIC_1164.all;
- Entity MyReg is
- port(clk,clr: in STD_LOGIC;
- D: in STD_LOGIC_VECTOR(3 downto 0);
- Q: out STD_LOGIC_VECTOR(3 downto 0));
- end MyReg;
- Architecture behavioral of MyReg is
- begin
- process(clk, clr)
- begin
- if clr='1' then
- Q<=(others=>'0');
- else if rising_edge(clk) then \\va anche bene (clk'event and clk='1') invece di rising_edge(clk)
- Q<=D;
- end if;
- end process;
- end behavioral;
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