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Jul 12th, 2019
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  1. module freq(CLK, A1, A2);
  2.    parameter COUNTER_LIMIT = 200_000_000;
  3.  
  4.    localparam WIDTH = $clog2(COUNTER_LIMIT) - 1;
  5.  
  6.    input wire CLK;
  7.    input wire A1;
  8.    output wire A2;
  9.  
  10.    reg [WIDTH:0] counter;
  11.    reg [WIDTH:0] pulses;
  12.    reg result;
  13.  
  14.    reg pulse_meta;
  15.    reg pulse_current;
  16.    reg pulse_prev;
  17.  
  18.    initial counter = COUNTER_LIMIT;
  19.    initial pulses = 0;
  20.    initial result = 0;
  21.    initial pulse_meta = 0;
  22.    initial pulse_current = 0;
  23.    initial pulse_prev = 0;
  24.  
  25.    assign A2 = result;
  26.  
  27.    always @(posedge CLK) begin
  28.      {pulse_prev, pulse_current, pulse_meta} <= {pulse_current, pulse_meta, A1};
  29.      if (counter == 0)
  30.        pulses <= 0;
  31.      else if (pulse_current != pulse_prev)
  32.        pulses <= pulses + 1;
  33.    end
  34.  
  35.    always @(posedge CLK) begin
  36.      if (counter == 0)
  37.      begin
  38.         counter <= COUNTER_LIMIT;
  39.         result <= ^pulses;
  40.      end
  41.      else
  42.         counter <= counter - 1;
  43.    end
  44. endmodule
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