// full_machine: execute a series of MIPS instructions from an instruction cache
//
// except (output) - set to 1 when an unrecognized instruction is to be executed.
// clock   (input) - the clock signal
// reset   (input) - set to 1 to set all registers to zero, set to 0 for normal execution.

module full_machine(except, clock, reset);
    output      except;
    input       clock, reset;

    wire [31:0] inst;
    wire [31:0] PC;
    wire [31:0] nextPC, iPC, jPC, branch_offset, imm32;
    wire rd_src, alu_src2, wr_enable;
    wire [2:0] alu_op;
    wire [4:0] Rdest;
    wire [31:0] rd_Data, addr;
    wire zero, negative, overflow;
    wire dataOtI;
    wire [1:0] control_type;
    wire       mem_read, word_we, byte_we, byte_load, slt, lui, addm;
    // ******** PC Register and Instruction Memory ******* //
    // DO NOT comment out or rename this module
    // or the test bench will break
    register #(32) PC_reg(PC, nextPC, clock, 1'b1, reset);
    alu32 alu(iPC, zero, negative, overflow, PC, 32'b0100, 3'b010);

    // DO NOT comment out or rename this module
    // or the test bench will break
    wire [31:0] rsData, rtData, B;
    instruction_memory im(inst, PC[31:2]);
    assign imm32 = { {16{inst[15]}}, inst[15:0] };
    assign branch_offset = imm32 << 2;
    alu32 alu1(jPC, zero, negative, overflow, iPC, branch_offset, 3'b010);

    // ************************************************** //
    // ********** Register ************** //

    // DO NOT comment out or rename this module
    // or the test bench will break
    mips_decode mpd(alu_op, rd_src, alu_src2, wr_enable, except, control_type,
                    mem_read, word_we, byte_we, byte_load, slt, lui, addm,
                    inst[31:26], inst[5:0], zero);
    mux4v #(32) nextPCMux(nextPC, iPC, jPC, { PC[31:28], {28{1'b0}}}, rsData,
                                control_type);
    mux2v #(5)  m2(Rdest, inst[15:11], inst[20:16], rd_src);
    regfile rf(rsData, rtData, inst[25:21], inst[20:16], Rdest, rd_Data,
                wr_enable, clock, reset);
    //mux2v #(32) rdMux(rd_Data, {inst[15:0], 16'b0}, dataOtI, lui);
    // ********** ********* ************** //
    // ********** Data Memory ************ //
    wire [31:0] data_out;
    mux2v #(32) m2_1(B, rtData, imm32, alu_src2);
    alu32 pDMALU(addr, zero, negative, overflow, rsData, B, alu_op);
    data_mem dm(data_out, addr, rtData, word_we, byte_we, clock, reset);
    /* add other modules */
    // ********************************** //
    // ********** Whole Lotta Mux's ******//
    wire [7:0] riData8, riData132;
    wire [31:0] riData232, riData332, riData3532;
    mux4v #(8) oMux(riData132, data_out[31:24], data_out[23:16], data_out[15:8],
                    data_out[7:0], addr[1:0]);
    mux2v #(32) fMux(riData232, data_out, {24'b0, riData132}, byte_load);
    mux2v #(32) gMux(riData3532, addr, {31'b0, negative}, slt);
    mux2v #(32) mMux(riData332, riData3532, riData232, mem_read);
    mux2v #(32) fmMux(rd_Data, riData332, {16'b0, inst[15:0]}, lui);

endmodule // full_machine