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Jul 3rd, 2017
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  1. module knight_rider(
  2.     input clk, rst,
  3.     output [7:0] r
  4. );
  5.  
  6. // másodperces engedélyező jel
  7. reg [25:0] cntr = 0;
  8. wire en = (cntr == 9/*49999999*/); // 1 Hz
  9.  
  10. always @(posedge clk)
  11.        if (rst | en)
  12.                cntr <= 0;
  13.        else
  14.                cntr <= cntr + 1;
  15.  
  16.  
  17. reg [7:0] shr = 8'b00000001;
  18. reg dir = 0;
  19.  
  20. wire first = (shr[1] == 1);
  21. wire last  = (shr[6] == 1);
  22.  
  23. // shiftelés iránya
  24. always @(posedge clk)
  25.   if ( rst )
  26.     dir <= 0;
  27.   else if ( en )
  28.     if ( (first & dir) | (last & !dir) )
  29.       dir <= ~dir;
  30.  
  31. // shiftelés
  32. always @(posedge clk)
  33.   if ( rst )
  34.     shr <= 8'b00000001;
  35.   else if ( en )
  36.     if ( dir ) // jobbra
  37.       shr <= { shr[0], shr[7:1] };
  38.     else       // balra
  39.       shr <= { shr[6:0], shr[7] };
  40.  
  41. assign r = shr;
  42.  
  43. endmodule
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