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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    10:05:04 10/01/2010
  6. -- Design Name:
  7. -- Module Name:    data_memory - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use IEEE.STD_LOGIC_ARITH.ALL;
  23. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  24.  
  25. ---- Uncomment the following library declaration if instantiating
  26. ---- any Xilinx primitives in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29.  
  30. entity data_memory is
  31.     Port ( address : in  STD_LOGIC_VECTOR (31 downto 0);
  32.            write_data : in  STD_LOGIC_VECTOR (31 downto 0);
  33.            read_enable : in  STD_LOGIC;
  34.            write_enable : in  STD_LOGIC;
  35. --            CLK: in STD_LOGIC;
  36.            read_data : out  STD_LOGIC_VECTOR (31 downto 0));
  37. end data_memory;
  38.  
  39. architecture Behavioral of data_memory is
  40.  
  41. begin
  42.  data_mem:
  43.   process(address, write_enable, read_enable, write_data)--, clk)
  44. --   process(clk)
  45.       subtype word is std_logic_vector(31 downto 0);
  46.       type mem_array  is array(natural range <>) of word;
  47.       variable memory: mem_array(0 to 3) :=
  48.           ("10000000000000000000000000000000",
  49.            "00000000000000000000000000000000",
  50.            "00000000000000000000000000000000",
  51.            others=>(others=>'0'));
  52.       variable word_addr : natural;  -- byte addr/4
  53.       begin
  54. --          if(clk'event and clk = '1') then
  55.               if read_enable='1' and address(31) = '0' then
  56.                  word_addr := conv_integer(address(3 downto 2));  -- small mem
  57.                  read_data <= memory(word_addr) after 250 ps;
  58.               else
  59.                  read_data <= "00000000000000000000000000000000";
  60.               end if;
  61.               if write_enable='1' and address (31) = '0' then
  62.                  word_addr := conv_integer(address(3 downto 2));
  63.                  memory(word_addr) := write_data;
  64.               end if;
  65. --          end if;
  66.     end process data_mem;
  67.  
  68. end Behavioral;
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