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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 10:05:04 10/01/2010
- -- Design Name:
- -- Module Name: data_memory - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- ---- Uncomment the following library declaration if instantiating
- ---- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity data_memory is
- Port ( address : in STD_LOGIC_VECTOR (31 downto 0);
- write_data : in STD_LOGIC_VECTOR (31 downto 0);
- read_enable : in STD_LOGIC;
- write_enable : in STD_LOGIC;
- -- CLK: in STD_LOGIC;
- read_data : out STD_LOGIC_VECTOR (31 downto 0));
- end data_memory;
- architecture Behavioral of data_memory is
- begin
- data_mem:
- process(address, write_enable, read_enable, write_data)--, clk)
- -- process(clk)
- subtype word is std_logic_vector(31 downto 0);
- type mem_array is array(natural range <>) of word;
- variable memory: mem_array(0 to 3) :=
- ("10000000000000000000000000000000",
- "00000000000000000000000000000000",
- "00000000000000000000000000000000",
- others=>(others=>'0'));
- variable word_addr : natural; -- byte addr/4
- begin
- -- if(clk'event and clk = '1') then
- if read_enable='1' and address(31) = '0' then
- word_addr := conv_integer(address(3 downto 2)); -- small mem
- read_data <= memory(word_addr) after 250 ps;
- else
- read_data <= "00000000000000000000000000000000";
- end if;
- if write_enable='1' and address (31) = '0' then
- word_addr := conv_integer(address(3 downto 2));
- memory(word_addr) := write_data;
- end if;
- -- end if;
- end process data_mem;
- end Behavioral;
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