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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company: IS Enerprises
- // Engineer: Letuchiy Sergey V.
- //
- // Create Date: 16:55:03 10/07/2018
- // Design Name: Example of simple counter
- // Module Name: Simple counter module
- // Project Name: Package of examples
- // Target Devices: SP-6 xc6slx9
- // Tool versions: ISE - 14.7
- // Description: Package of examples for developer board SPARTAN-6
- //
- // Dependencies:
- //
- // Revision: 0000.0001.0001
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module Counter_Ver1 #(parameter DIGITA = 24)
- (
- input clk,
- output CARRYA,
- output CARRYB,
- output CARRYC,
- output CARRYD
- );
- // 25 wires.
- wire [DIGITA:0]add;
- // Register counter.
- reg [DIGITA:0]RG = {(DIGITA){1'b0}};
- assign add[DIGITA:0] = RG[DIGITA:0] + 1'b1;
- assign CARRYA = RG[DIGITA];
- assign CARRYB = !RG[DIGITA];
- assign CARRYC = RG[DIGITA];
- assign CARRYD = !RG[DIGITA];
- // Ticker one second.
- always@(posedge clk) begin
- RG[DIGITA:0] <= add[DIGITA:0];
- end
- endmodule
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